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65 条记录 (耗时 0.041 秒)

    Low noise amplification circuit
    52.
    发明授权
    Low noise amplification circuit 有权
    低噪声放大电路

    公开(公告)号：US07596361B2

    公开(公告)日：2009-09-29

    申请号：US11442326

    申请日：2006-05-30

    申请人： Sadao Matsushima ,  Toshihide Fukuchi ,  Yuji Nakagawa ,  Shiro Koide

    发明人： Sadao Matsushima ,  Toshihide Fukuchi ,  Yuji Nakagawa ,  Shiro Koide

    IPC分类号： H04B1/10 ,  H04B1/16

    CPC分类号： H04B1/18

    摘要： A low noise amplification circuit comprises a low noise amplifier and a filter coupled to the input terminal of the low noise amplifier. The low noise amplifier comprises an amplifying element and a matching input circuit coupled to the input terminal of the amplifying element. When gamma.sub.s shows a reflection factor in the case that signals flow from the input terminal of the amplifying element to the output terminal of the matching input circuit, impedance conversion for setting the gamma.sub.s at a desired value is made entirely or in part by means of setting the output impedance of the filter at the value different from that of characteristic impedance.

    摘要翻译： 低噪声放大电路包括低噪声放大器和耦合到低噪声放大器的输入端的滤波器。 低噪声放大器包括放大元件和耦合到放大元件的输入端的匹配输入电路。 当γ.sub.s在信号从放大元件的输入端流向匹配输入电路的输出端的情况下显示出反射因子时，将γ.sub.s设定为期望值的阻抗转换 完全或部分地通过将滤波器的输出阻抗设置在与特性阻抗不同的值。

    SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD FOR THE SAME
    53.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD FOR THE SAME 失效
    半导体存储器件及其相关方法

    公开(公告)号：US20090073793A1

    公开(公告)日：2009-03-19

    申请号：US12273269

    申请日：2008-11-18

    申请人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

    发明人： Hajime Sato ,  Yuji Nakagawa ,  Satoru Kawamoto

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/02 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4068

    摘要： A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.

    摘要翻译： 用于半导体存储器件的刷新方法具有高抗噪性，较低的功耗和较低的成本。 在自刷新模式下未被选择的一个或多个存储单元块的所有字线被控制为具有基本上处于地平面的浮动电位。 即使当字线和位线短路时，该控制也可以防止可能由噪声引起的存储单元信息的破坏，并且还防止漏电流的产生。 不需要用于防止产生泄漏电流的保险丝等，从而实现较低的成本。

    Low noise amplification circuit
    56.
    发明申请
    Low noise amplification circuit 有权

    公开(公告)号：US20060270380A1

    公开(公告)日：2006-11-30

    申请号：US11442326

    申请日：2006-05-30

    申请人： Sadao Matsushima ,  Toshihide Fukuchi ,  Yuji Nakagawa ,  Shiro Koide

    发明人： Sadao Matsushima ,  Toshihide Fukuchi ,  Yuji Nakagawa ,  Shiro Koide

    IPC分类号： H04B1/16

    CPC分类号： H04B1/18

    摘要： A low noise amplification circuit comprises a low noise amplifier and a filter coupled to the input terminal of the low noise amplifier. The low noise amplifier comprises an amplifying element and a matching input circuit coupled to the input terminal of the amplifying element. When gamma.sub.s shows a reflection factor in the case that signals flow from the input terminal of the amplifying element to the output terminal of the matching input circuit, impedance conversion for setting the gamma.sub.s at a desired value is made entirely or in part by means of setting the output impedance of the filter at the value different from that of characteristic impedance.

    Battery having a sheet current collector fluid-tightly separating basic cells
    57.
    发明授权
    Battery having a sheet current collector fluid-tightly separating basic cells 有权
    具有片状集电器的电池流体密封地分离碱性电池

    公开(公告)号：US06998190B2

    公开(公告)日：2006-02-14

    申请号：US10346102

    申请日：2003-01-17

    申请人： Tomoki Nobuta ,  Toshihiko Nishiyama ,  Hiroyuki Kamisuki ,  Gaku Harada ,  Masato Kurosaki ,  Yuji Nakagawa ,  Masaya Mitani

    发明人： Tomoki Nobuta ,  Toshihiko Nishiyama ,  Hiroyuki Kamisuki ,  Gaku Harada ,  Masato Kurosaki ,  Yuji Nakagawa ,  Masaya Mitani

    IPC分类号： H01M6/46

    CPC分类号： H01G9/155 ,  H01G9/10 ,  H01M2/0212 ,  H01M6/12 ,  H01M10/0436 ,  Y02E60/13

    摘要： A small battery and an electric double layer capacitor exhibit adequate cell voltage and capacitor withstand voltage. Specifically, the battery or electric double layer capacitor includes basic cells having a pair of electrodes oppositely laminated via the separator, and an electrolyte are packaged in a resin sheet package. The basic cells are laminated in series via a sheet current collector. The sheet current collector extends to an edge of the resin sheet package around the periphery of the basic cells laminated on both sides of the current collector. The sheet current collector is glued or fused to the resin sheet in its edge. The adjacent basic cells via the sheet current collector are fluid-tightly separated within the resin sheet package.

    摘要翻译： 小电池和双电层电容器表现出足够的电池电压和电容器耐受电压。 具体地，电池或双电层电容器包括具有通过隔板相对地层叠的一对电极的碱性电池，并且将电解质包装在树脂片封装中。 碱性电池通过片状集电器串联层叠。 片状集电体延伸到层叠在集电体两侧的基本电池的周围的树脂片包装的边缘。 片状集电器在其边缘上胶合或熔合到树脂片。 通过片状集电器的相邻基本电池在树脂片封装内流体密封地分离。

    Semiconductor memory device and method for selecting multiple word lines in a semiconductor memory device
    60.
    发明授权
    Semiconductor memory device and method for selecting multiple word lines in a semiconductor memory device 失效

    公开(公告)号：US06788610B2

    公开(公告)日：2004-09-07

    申请号：US10365504

    申请日：2003-02-13

    申请人： Yuji Nakagawa

    发明人： Yuji Nakagawa

    IPC分类号： G11C800

    CPC分类号： G11C29/34

    摘要： A semiconductor memory device that reduces the time for conducting a multiple word line selection test and operates stably. The semiconductor memory device includes memory cell blocks, row decoders, sense amps, block control circuits, and sense amp drive circuits. Each block control circuit generates a reset signal. The reset signal is used to select the word lines with the row decoders at timings that differ between the blocks. Each block control circuit provides the reset signal to the associated row decoder. The block control circuit also provides the reset signal to the associated sense amp drive circuit so that the sense amps are inactivated at timings that differ between the blocks.