公开(公告)号：US08416018B2

公开(公告)日：2013-04-09

申请号：US13058008

申请日：2009-11-04

申请人： Kazuhisa Yamauchi ,  Hidenori Yukawa ,  Akira Inoue ,  Atsushi Yamamoto ,  Koichi Fujisaki ,  Hiroomi Ueda

发明人： Kazuhisa Yamauchi ,  Hidenori Yukawa ,  Akira Inoue ,  Atsushi Yamamoto ,  Koichi Fujisaki ,  Hiroomi Ueda

IPC分类号： H03F3/68

CPC分类号： H03F1/42 ,  H03F1/32 ,  H03F3/191 ,  H03F3/211 ,  H03F3/24 ,  H03F2200/192 ,  H03F2200/195 ,  H03F2200/198 ,  H03F2200/201 ,  H03F2200/204 ,  H03F2200/207

摘要： A variable frequency amplifier includes a main amplifier system 4 for amplifying one of signals into which an input signal is split by a directional coupler 3 to output the amplified signal, and an injection amplifier system 9 for adjusting at least one of the amplitude and phase of the other one of the signals into which the input signal is split by the directional coupler 3 according to a setting provided thereto from outside the variable frequency amplifier, and for amplifying the other signal and injecting this amplified signal into an output side of the main amplifier system 4.

摘要翻译： 可变频放大器包括：主放大器系统4，用于放大由定向耦合器3输入信号被分离的信号之一以输出放大信号;以及注入放大器系统9，用于调节幅度和相位中的至少一个 根据从可变频放大器的外部提供的设置，由定向耦合器3将输入信号分离的信号中的另一个，并且用于放大另一信号并将该放大信号注入到主放大器的输出侧 系统4

公开(公告)号：US20120246503A1

公开(公告)日：2012-09-27

申请号：US13420814

申请日：2012-03-15

申请人： Koichi Fujisaki ,  Tatsunori Kanai ,  Tetsuro Kimura ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki ,  Akihiro Shibata

发明人： Koichi Fujisaki ,  Tatsunori Kanai ,  Tetsuro Kimura ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki ,  Akihiro Shibata

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3212 ,  Y02D10/174

摘要： According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor.

摘要翻译： 根据一个实施例，信息处理设备包括处理器，非易失性存储单元，接收单元，判断单元和发送单元。 接收单元从处理器接收关于存储单元的可访问性的查询。 判断单元在接收到询问后判断存储单元是否可以基于开始向存储单元供电的启动时间段和存储单元的激活而启动。 发送单元将由判断单元获得的判断结果发送给处理器。

公开(公告)号：US20110246791A1

公开(公告)日：2011-10-06

申请号：US12880513

申请日：2010-09-13

申请人： Toru Kambayashi ,  Taku Kato ,  Hiroshi Sukegawa ,  Yoshihiko Hirose ,  Koichi Fujisaki

发明人： Toru Kambayashi ,  Taku Kato ,  Hiroshi Sukegawa ,  Yoshihiko Hirose ,  Koichi Fujisaki

IPC分类号： G06F12/14

CPC分类号： G06F12/1408 ,  G06F21/445 ,  G06F21/79 ,  G06F2221/2107

摘要： According to one embodiment, a memory chip, which is connected to a writing device that writes data and to a reading device that reads data, includes: a memory including a first area that is a predetermined data storage area; a second encryption key generating unit that receives second key information stored in the reading device and generates a third key; and a sending unit that transmits, to the reading device, second encrypted data obtained by encrypting data stored in the memory using the third key. The second encrypted data is received by the reading device and is decrypted by using a fourth key that is stored in the reading device and that corresponds to the third key.

摘要翻译： 根据一个实施例，连接到写入数据的写入装置和读取数据的读取装置的存储器芯片包括：存储器，包括作为预定数据存储区域的第一区域; 第二加密密钥生成单元，接收存储在读取装置中的第二密钥信息，生成第三密钥; 以及发送单元，其向所述读取装置发送通过使用所述第三密钥加密存储在所述存储器中的数据而获得的第二加密数据。 第二加密数据由读取装置接收，并且通过使用存储在读取装置中并对应于第三密钥的第四密钥进行解密。

公开(公告)号：US20100079210A1

公开(公告)日：2010-04-01

申请号：US12518664

申请日：2007-12-05

申请人： Kazuhisa Yamauchi ,  Yuji Sakai ,  Koichi Fujisaki ,  Akira Inoue

发明人： Kazuhisa Yamauchi ,  Yuji Sakai ,  Koichi Fujisaki ,  Akira Inoue

IPC分类号： H03F1/07

CPC分类号： H03F1/0238 ,  H03F1/0244 ,  H03F1/0288

摘要： Provided is a power amplification device including: a DC power supply that outputs a drain voltage; a Doherty amplifier including a carrier amplifier and a peak amplifier, which are connected in parallel, and amplifies an RF signal; a voltage control circuit that outputs a first instruction to output a low voltage when an output power is equal to or lower than a given value, and outputs a second instruction to output a high voltage when the output power is larger than the given value; and a voltage converter circuit that converts the drain voltage to a voltage lower than the drain voltage and applies the converted voltage to drain terminals of the carrier amplifier and the peak amplifier according to the first instruction, and applies the drain voltage directly to the drain terminals of the carrier amplifier and the peak amplifier according to the second instruction.

摘要翻译： 提供了一种功率放大装置，包括：输出漏极电压的直流电源; 包括并联连接的载波放大器和峰值放大器的Doherty放大器，并放大RF信号; 电压控制电路，当输出功率等于或低于给定值时，输出第一指令以输出低电压，并且当输出功率大于给定值时输出第二指令以输出高电压; 以及电压转换器电路，其将漏极电压转换为低于漏极电压的电压，并根据第一指令将转换的电压施加到载波放大器和峰值放大器的漏极端子，并将漏极电压直接施加到漏极端子 的载波放大器和峰值放大器。

公开(公告)号：US20050249029A1

公开(公告)日：2005-11-10

申请号：US11180558

申请日：2005-07-14

申请人： Koichi Fujisaki ,  Kentaro Nakajima ,  Takeshi Chujoh ,  Yasuhiro Taniguchi

发明人： Koichi Fujisaki ,  Kentaro Nakajima ,  Takeshi Chujoh ,  Yasuhiro Taniguchi

IPC分类号： G06F12/02 ,  G11C8/10 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C5/00

CPC分类号： G06F12/0207 ,  G11C8/10

摘要： A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner data is read from a magnetoresistive memory module in both row and column directions.

摘要翻译： 存储单元模块包括由M列×N行的存储器单元形成的存储单元阵列。 每个存储单元包括具有半导体元件的磁阻元件或磁阻元件。 存储器模块包括通过列方向访问存储单元阵列的第一存取装置和通过行方向访问存储单元阵列的第二存取装置。 以这种方式，在行和列方向上从磁阻存储器模块读取数据。