公开(公告)号：US20060174251A1

公开(公告)日：2006-08-03

申请号：US11050483

申请日：2005-02-03

Applicant: Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts ,  John Chiang

Inventor： Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts ,  John Chiang

IPC: G06F9/46

CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901

Abstract: Method for managing a data transmit queue, for use with a host and a network interface device. Roughly described, the host writes data buffer descriptors into a transmit descriptor queue, and the network interface device writes events to notify the host when it has completed processing of a transmit data buffer. Each of the transmit completion event descriptors notify the host of completion of a plurality of the transmit data buffers.

公开(公告)号：US20060173970A1

公开(公告)日：2006-08-03

申请号：US11050474

申请日：2005-02-03

Applicant: Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

Inventor： Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

IPC: G06F15/167

CPC classification number: G06F9/4812 ,  G06F13/28 ,  G06F13/32 ,  G06F13/385

Abstract: Roughly described, method for managing data transmission between a host subsystem and a network interface device, in which the host writes data buffer descriptors into a DMA descriptor queue, and the network interface device writes completion events to notify the host when it has completed processing of data buffers. Each of the completion event descriptors notify the host of completion of data transfer between the NIC and one or more of the data buffers, and can also embed a queue empty notification inside the completion event.

Abstract translation: 粗略地描述了用于管理主机子系统和网络接口设备之间的数据传输的方法，其中主机将数据缓冲器描述符写入DMA描述符队列，并且网络接口设备写入完成事件以在主机完成处理 数据缓冲区。 每个完成事件描述符通知主机NIC和一个或多个数据缓冲区之间的数据传输完成，并且还可以在完成事件中嵌入队列空通知。

公开(公告)号：US20050183093A1

公开(公告)日：2005-08-18

申请号：US11050476

申请日：2005-02-03

Applicant: Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

Inventor： Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

IPC: G06F9/46 ,  G06F13/38 ,  G11C5/00 ,  H04L29/00

CPC classification number: G06F13/24 ,  G06F13/385 ,  G06F13/4282

Abstract: Method of managing interaction between a host subsystem and a peripheral device. Roughly described, the peripheral device writes an event into an individual event queue, and in conjunction therewith, also writes a wakeup event into an intermediary event queue. The wakeup event identifies the individual event queue. The host subsystem, in response to retrieval of the wakeup event from the intermediary event queue, activates an individual event handler to consume events from the individual event queue.

Abstract translation: 管理主机子系统和外围设备之间的交互的方法。 粗略描述，外围设备将事件写入单个事件队列中，并且与之结合，还将唤醒事件写入中间事件队列。 唤醒事件标识单个事件队列。 响应于从中间事件队列检索唤醒事件，主机子系统激活单独的事件处理程序以从各个事件队列消耗事件。

公开(公告)号：US20050177657A1

公开(公告)日：2005-08-11

申请号：US11050419

申请日：2005-02-03

Applicant: Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

Inventor： Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

IPC: G06F9/46 ,  G06F13/38 ,  G11C5/00 ,  H04L29/00

CPC classification number: G06F13/24 ,  G06F13/385 ,  G06F13/4282

Abstract: Method for managing a queue in host memory for use with a peripheral device. Roughly described, the host makes a determination of the availability of space in the queue for writing new entries, in dependence upon historical knowledge of the number of queue entries that the host has authorized the device to write, and the number of entries that the host has consumed. In dependence on that determination, the host authorizes the device to write a limited number of new entries into the queue. The device writes entries into the queue dependence upon the number authorized. The host maintains a read pointer into the queue but does not need to maintain a write pointer, and the peripheral device maintains a write pointer into the queue but does not need to maintain a read pointer.

Abstract translation: 用于管理主机存储器中用于外围设备的队列的方法。 粗略地描述，主机根据主机授权设备写入的队列条目的数量的历史知识以及主机的条目数量来确定队列中用于写入新条目的空间的可用性 已消耗 根据该确定，主机授权设备将有限数量的新条目写入队列。 设备根据授权的数量将条目写入队列。 主机将读指针保留在队列中，但不需要维护写指针，外围设备将写入指针保持在队列中，但不需要维护读指针。

公开(公告)号：US20050141160A1

公开(公告)日：2005-06-30

申请号：US11005533

申请日：2004-12-06

Applicant: Yun Ma ,  Ching Yu

Inventor： Yun Ma ,  Ching Yu

IPC: H01C7/13 ,  H02H9/02

CPC classification number: H01C7/13

Abstract: An over-current protection apparatus comprises a plurality of over-current protection devices and a bonding sheet. Each over-current protection device comprises at least one current-sensitive element, two outer electrode layers and at least one insulating layer disposed on a surface of the current-sensitive element. The bonding sheet penetrates and connects the plurality of over-current protection devices, and is disposed on a surface of the at least one current-sensitive element for insulation.

Abstract translation: 过电流保护装置包括多个过电流保护装置和接合片。 每个过电流保护装置包括至少一个电流敏感元件，两个外部电极层和设置在电流敏感元件的表面上的至少一个绝缘层。 接合片渗透并连接多个过流保护装置，并且设置在至少一个电流敏感元件的表面上用于绝缘。

公开(公告)号：US06904043B1

公开(公告)日：2005-06-07

申请号：US09316072

申请日：1999-05-21

Applicant: Shashank Merchant ,  Ching Yu

Inventor： Shashank Merchant ,  Ching Yu

IPC: H04L12/56 ,  H04L29/06 ,  H04L12/28

CPC classification number: H04L49/25 ,  H04L49/205 ,  H04L49/254 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047 ,  H04L49/9073 ,  H04L49/9089 ,  H04L69/22

Abstract: A network switch configured for switching data packets across multiple ports uses an internal memory to store frame headers for processing by decision making logic. The internal memory stores frame headers in a queue configured to store a number of the frame headers for each of the receive ports. A scheduler is included for facilitating the transfer the data from the queues to the decision making logic according to a predetermined priority. The scheduler is also able allocate the time slots in accordance with data traffic at the corresponding receive ports to maximize data throughput.

Abstract translation: 配置用于跨多个端口切换数据包的网络交换机使用内部存储器来存储用于由决策逻辑进行处理的帧头。 内部存储器存储队列中的帧头，被配置为存储每个接收端口的多个帧头。 包括调度器，以便于根据预定优先级将数据从队列传送到决策逻辑。 调度器还可以根据相应接收端口处的数据流量来分配时隙以最大化数据吞吐量。

公开(公告)号：US06769055B1

公开(公告)日：2004-07-27

申请号：US09263948

申请日：1999-03-08

Applicant: Eric Tsin-Ho Leung ,  Ching Yu

Inventor： Eric Tsin-Ho Leung ,  Ching Yu

IPC: G06F1200

CPC classification number: H04L47/24 ,  H04L49/15 ,  H04L49/3036 ,  H04L49/351 ,  H04L49/90

Abstract: A memory address generator for a multiport data communication system storing received data packets in a memory having a plurality of storage areas. The data communication system has a plurality of receive ports receiving the data packets and a queue of addresses of a plurality of storage areas in the memory available for storing the received data packets. The address generator generates memory addresses to store the received data packets in the plurality of storage areas of the memory and includes first and second registers. The first register receives an address from the queue of addresses and provides a first part of the memory address, and the second register counts write cycles to the memory and provides the count result as a second part of the memory address.

Abstract translation: 一种用于多端口数据通信系统的存储器地址发生器，其将接收到的数据分组存储在具有多个存储区域的存储器中。 数据通信系统具有接收数据分组的多个接收端口和可用于存储接收到的数据分组的存储器中的多个存储区域的地址队列。 地址生成器生成存储器地址以将接收到的数据分组存储在存储器的多个存储区域中，并且包括第一和第二寄存器。 第一个寄存器从地址队列接收地址，并提供存储器地址的第一部分，第二个寄存器对存储器计数写入周期，并将计数结果作为存储器地址的第二部分提供。

公开(公告)号：US06725270B1

公开(公告)日：2004-04-20

申请号：US09316184

申请日：1999-05-21

Applicant: Ching Yu ,  Bahadir Erimli ,  Jenny Liu Fischer ,  Peter Chow

Inventor： Ching Yu ,  Bahadir Erimli ,  Jenny Liu Fischer ,  Peter Chow

IPC: G06F1516

CPC classification number: H04L12/413 ,  H04L67/10 ,  H04L67/14 ,  H04L69/329

Abstract: A network switch having switch ports for communication of data packets with respective computer network nodes according to CSMA/CD protocol that resets a retry counter for counting data packet transmission attempts within any one of the respective switch ports if backpressure is asserted by that port. A retry limit value for the retry counter is selectively modified according to programmed information to ensure that the total number of retrys does not exceed a maximum total number of allowable retrys. Resetting the retry counter within a port after assertion of backpressure affords the port a greater probability of transmitting earlier under the CSMA/CD protocol, thus more quickly relieving congestion which may occur in the network switch. Selective modification of the retry limit value according to programmed information adds flexibility to vary the maximum total number of allowable retrys based upon current network switch conditions or the priority of a particular data packet.

Abstract translation: 具有用于根据CSMA / CD协议与数据分组与各个计算机网络节点进行通信的交换机端口的网络交换机，其复位重试计数器，用于如果该端口的背压被断言，则用于计数任何一个相应交换机端口内的数据分组传输尝试。 重试计数器的重试限制值根据编程信息进行选择性修改，以确保反射总数不超过允许的最大总数。 在断开背压之后重置端口中的重试计数器，使得端口在CSMA / CD协议下较早发送的可能性更大，从而更快地减轻网络交换机中可能发生的拥塞。 根据编程信息对重试限制值的选择性修改增加了灵活性，以根据当前网络切换条件或特定数据包的优先级来改变允许retrys的最大总数。

公开(公告)号：US06526370B1

公开(公告)日：2003-02-25

申请号：US09244416

申请日：1999-02-04

Applicant: Ching Yu ,  Jerry Kuo ,  Jeffrey Dwork ,  John M. Chiang

Inventor： Ching Yu ,  Jerry Kuo ,  Jeffrey Dwork ,  John M. Chiang

IPC: G06F1130

CPC classification number: H04L43/00 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/88

Abstract: A system for accumulating data relating to performance parameters of a data communication system is provided in order to determine average values of these parameters. The system comprises multiple registers used for calculating average values of particular performance parameters, such as bus latency, interrupt latency, receive service routine time, and receive frame copy time. Each of the registers contains an event counter and a timer. The event counter increments upon occurrence of an event relating to the performance parameter accumulated by the corresponding register. The timer is activated by the occurrence of the event, and increments at a predetermined rate until the event comes to an end. The timer resumes incrementing when the next event occurs. As a result, the CPU is enabled to determine an average value of a particular parameter per an event relating to this parameter.

Abstract translation: 提供一种用于累积与数据通信系统的性能参数有关的数据的系统，以便确定这些参数的平均值。 该系统包括用于计算特定性能参数的平均值的多个寄存器，例如总线等待时间，中断延迟，接收服务程序时间和接收帧复制时间。 每个寄存器都包含一个事件计数器和一个定时器。 事件计数器在出现与相应寄存器累积的性能参数相关的事件时递增。 定时器由事件的发生激活，并以预定的速率递增直到事件结束。 当下一个事件发生时，定时器恢复递增。 结果，CPU能够确定与该参数相关的事件的特定参数的平均值。

公开(公告)号：US06424591B1

公开(公告)日：2002-07-23

申请号：US09321843

申请日：1999-05-28

Applicant: Ching Yu ,  Autumn Jane Niu

Inventor： Ching Yu ,  Autumn Jane Niu

IPC: G06F1200

CPC classification number: G06F13/1668 ,  G06F13/385

Abstract: A novel method of providing a host with assess to a buffer memory in a network interface in FIFO and SRAM modes of operation. A decoder decodes whether the host issues an SRAM-type access request or a FIFO-type access request to perform access to the buffer memory. In response to the FIFO-type access request, pointers to the memory are controlled so as to perform sequential addressing of the buffer memory. In response to the SRAM-type request, the pointers are controlled so as to perform random access addressing of the buffer memory.

Abstract translation: 一种提供主机评估FIFO和SRAM操作模式的网络接口中的缓冲存储器的新颖方法。 解码器解码主机是否发出SRAM类型的访问请求或FIFO类型的访问请求以执行对缓冲存储器的访问。 响应于FIFO型访问请求，控制指向存储器的指针，以便执行缓冲存储器的顺序寻址。 响应于SRAM类型请求，控制指针以便执行缓冲存储器的随机存取寻址。