公开(公告)号：US09729960B1

公开(公告)日：2017-08-08

申请号：US14297480

申请日：2014-06-05

Applicant: Avnera Corporation

Inventor： Manpreet Singh Khaira ,  Thomas Irrgang

IPC: H04R1/20 ,  H04R1/28

CPC classification number: H04R1/20 ,  G06F3/021 ,  H04R1/026 ,  H04R1/28 ,  H04R1/2803 ,  H04R1/2857 ,  H04R3/12 ,  H04R5/02 ,  H04R2205/021 ,  H04R2225/33 ,  H04R2400/03 ,  H04R2420/07 ,  H04R2430/01 ,  H04R2499/11 ,  H04S7/301

Abstract: An acoustic layer is added to a keyboard-type device including: enclosing walls, optionally—one or more microphones, a signal processing device, at least one audio transducer, and an acoustic waveguide. The acoustic layer adjoins one or more internal areas of a keyboard-type device. The signal processing device receives an internal signal from an electronic device either through wires or wirelessly. The signal processing device provides a directive sound enhancement of the audio input signals based on room acoustics, such as reverberation, echo, noise, delay, frequency response, and/or speaker-positional information that is determined by the signal processing device. The audio transducer device generates an audible audio output in response to an audio signal output from the signal processing device. The acoustic waveguide receives the audible audio output and generates an enhanced bass audio output from the acoustic waveguide.

公开(公告)号：US09728179B2

公开(公告)日：2017-08-08

申请号：US14885876

申请日：2015-10-16

Applicant: AVNERA CORPORATION

Inventor： Amit Kumar ,  Thomas Irrgang ,  Shankar Rathoud ,  Eric Sorensen

IPC: G10K11/178

CPC classification number: G10K11/178 ,  G10K11/17813 ,  G10K11/1788 ,  G10K11/17881 ,  G10K2210/1081 ,  G10K2210/3025 ,  G10K2210/3026 ,  G10K2210/3027 ,  G10K2210/3045 ,  G10K2210/3055 ,  G10K2210/3056 ,  G10K2210/3214 ,  G10K2210/504 ,  H04R1/1083 ,  H04R29/00 ,  H04R2460/01

Abstract: A method of calibrating an earphone may include: securing an ANC earphone to a calibration fixture, the calibration fixture including an ear model configured to support the ANC earphone, the ear model having an ear canal configured to anatomically resemble a human ear canal and a concha configured to anatomically resemble a human ear concha, the ear canal extending from the concha to an inner end of the ear canal; generating, with the ANC earphone, an audio signal based on a reference tone; determining a characteristic of the audio signal; comparing the characteristic of the audio signal to a previously determined reference characteristic; and adjusting a gain value of the ANC earphone based on the comparing. Additional methods and apparatus are also disclosed.

公开(公告)号：US09645786B2

公开(公告)日：2017-05-09

申请号：US14249696

申请日：2014-04-10

Applicant: Avnera Corporation

Inventor： Manpreet S. Khaira ,  Shawn O'Connor ,  Frank Prestrelski ,  Patrick Allen Quinn ,  Richard Andrew Sorensen ,  Eric Sorensen

IPC: G06F3/16 ,  G06F3/0346

CPC classification number: G06F3/162 ,  G06F3/017 ,  G06F3/0304 ,  G06F3/0346 ,  G06F3/0414 ,  G06F3/165 ,  G06F3/167 ,  G06F2200/1636 ,  H04R2201/02 ,  H04R2430/01

Abstract: A tabletop speaker system includes an amplifier, proximity and acceleration detectors, and a processor. The processor is operatively coupled to receive signals from the proximity and accelerometer detectors, and in response to the proximity and acceleration signals, activate various functions local to the tabletop speaker system to operate and control various behaviors or features of the tabletop speaker system. In this way, the tabletop speaker system can respond to user gestures for a very natural control interface.

公开(公告)号：US20140369529A1

公开(公告)日：2014-12-18

申请号：US13915805

申请日：2013-06-12

Applicant: Avnera Corporation

Inventor： Patrick Allen Quinn

IPC: H03F3/20

CPC classification number: H03F3/185 ,  H02M3/158 ,  H03F1/0233 ,  H03F3/181 ,  H03F3/217 ,  H03F3/2171 ,  H03F2200/03

Abstract: A device and method are disclosed for modulating a power converter based on an audio signal to directly drive a speaker with a differential audio output signal. A first modulation signal and a second modulation signal are generated based on an input audio signal so that the first and second modulation signals are complementary signals to each other. In one embodiment, a feedback signal, such as an acoustic feedback signal from the speaker, is also used to generate the first and second modulation signals. A power supply voltage is modulated with the first modulation signal to generate a first voltage signal. The power supply voltage is also modulated with the second modulation signal to generate a second voltage signal. The first and second voltage signals form a differential audio signal that is used to drive the speaker. Alternatively, the power converter can drive a speaker with a single-ended output signal.

Abstract translation: 公开了一种用于基于音频信号调制功率转换器以直接驱动具有差分音频输出信号的扬声器的装置和方法。 基于输入音频信号生成第一调制信号和第二调制信号，使得第一和第二调制信号彼此互补。 在一个实施例中，诸如来自扬声器的声反馈信号的反馈信号也用于产生第一和第二调制信号。 用第一调制信号调制电源电压以产生第一电压信号。 电源电压也用第二调制信号进行调制以产生第二电压信号。 第一和第二电压信号形成用于驱动扬声器的差分音频信号。 或者，功率转换器可以驱动具有单端输出信号的扬声器。

公开(公告)号：US20140270028A1

公开(公告)日：2014-09-18

申请号：US13800557

申请日：2013-03-13

Applicant: Avnera Corporation

Inventor： Samuel J. Peters, II ,  Eric P. Etheridge ,  Victor Lee Hanson ,  Alexander C. Stange

IPC: H04L7/027

CPC classification number: H04L7/027 ,  G06F13/4295 ,  H04L7/0029 ,  H04L7/02

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract translation: 用于从输入数据流中恢复数据而不输入输入采样电路与输入数据流的同步的系统和技术确定输入采样（或帧）的计数，而不产生频率锁定到输入数据流的信号。 产生包括大于或等于输入数据流的预期频率的频率的第一时钟。 响应于在输入数据流中接收到的采样，采样计数递增，并且响应于第二时钟信号递减。 如果采样计数器的采样计数不等于预定采样计数值，并且如果采样计数等于预定采样计数值则阻塞第一时钟信号，则通过传递第一时钟信号来产生第二时钟信号。

公开(公告)号：US08385133B2

公开(公告)日：2013-02-26

申请号：US11633901

申请日：2006-12-05

Applicant: Charles L. Saxe

Inventor： Charles L. Saxe

IPC: G11C7/10

CPC classification number: H04N5/907 ,  G11C7/1075 ,  G11C16/10 ,  G11C16/32 ,  G11C2216/14

Abstract: A flash memory system for an A/V player, utilizing a two-level round-robin write scheme upon N flash memory planes, enabling the A/V player to be loaded with data at a data throughput essentially N times the write throughput of one of the flash memory planes. The flash chips' memory cores and data registers, and the memory system's write buffers, can be kept fully utilized during data writing.

Abstract translation: 一种用于A / V播放器的闪存系统，在N个闪速存储器平面上利用两级循环写入方案，使A / V播放器能够以数据吞吐量基本上为N的一倍的写入吞吐量加载数据 的闪存盘。 闪存芯片的存储器内核和数据寄存器以及存储器系统的写入缓冲器可以在数据写入期间得到充分利用。

公开(公告)号：US07443200B2

公开(公告)日：2008-10-28

申请号：US11784489

申请日：2007-04-05

Applicant: Patrick A. Quinn ,  Wai L. Lee

Inventor： Patrick A. Quinn ,  Wai L. Lee

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: H03K19/018521

Abstract: A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power supply) transistors and a pair of voltage dividers to set the bias voltage at the gates of the high-side transistors, wherein one side of each voltage divider is coupled to the power supply node and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H- bridge.

Abstract translation: 提供基本上独立于输入信号的占空比的电平移位器的电路架构或拓扑结构包括场效应晶体管的H桥布置，连接到高电平的栅极的一对电容耦合的输入端子， （即，连接到正电源）晶体管和一对分压器，以在高侧晶体管的栅极处设置偏置电压，其中每个分压器的一侧耦合到电源节点，而另一侧耦合到电源节点 每个分压器的一侧交叉耦合到H桥的相对侧的输出节点。

公开(公告)号：US20070182616A1

公开(公告)日：2007-08-09

申请号：US11784489

申请日：2007-04-05

Applicant: Patrick Quinn ,  Wai Lee

Inventor： Patrick Quinn ,  Wai Lee

IPC: H03M1/78

CPC classification number: H03K19/018521

Abstract: A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power supply) transistors and a pair of voltage dividers to set the bias voltage at the gates of the high-side transistors, wherein one side of each voltage divider is coupled to the power supply node and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H- bridge.

Abstract translation: 提供基本上独立于输入信号的占空比的电平移位器的电路架构或拓扑结构包括场效应晶体管的H桥布置，连接到高电平的栅极的一对电容耦合的输入端子， （即，连接到正电源）晶体管和一对分压器，以在高侧晶体管的栅极处设置偏置电压，其中每个分压器的一侧耦合到电源节点，而另一侧耦合到电源节点 每个分压器的一侧交叉耦合到H桥的相对侧的输出节点。

公开(公告)号：US11677383B2

公开(公告)日：2023-06-13

申请号：US16296669

申请日：2019-03-08

Applicant: AVNERA CORPORATION

Inventor： Xudong Zhao

IPC: G10L21/0316 ,  H03H17/06 ,  H03M13/33 ,  H03M13/00 ,  H03M13/27 ,  H03M7/00 ,  H03M5/00 ,  G10L21/0356 ,  H03H17/02 ,  G10L19/24 ,  G10L19/00

CPC classification number: H03H17/0628 ,  G10L21/0316 ,  G10L21/0356 ,  H03H17/028 ,  H03M5/00 ,  H03M7/00 ,  H03M13/00 ,  H03M13/27 ,  H03M13/33 ,  G10L19/00 ,  G10L19/24 ,  G10L2019/001

Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

公开(公告)号：US11611822B2

公开(公告)日：2023-03-21

申请号：US17806295

申请日：2022-06-10

Applicant: AVNERA CORPORATION

Inventor： Michael Jon Wurtz ,  Amit Kumar ,  Jiajin An

IPC: H04R1/10 ,  H04R29/00 ,  H04R3/04 ,  H04R1/08 ,  G10K11/178 ,  H03F13/00 ,  H03G7/00 ,  H03F3/181 ,  H03F3/60

Abstract: A method of operating a headphone configured to be removed from and placed in close proximity to a user's ear can include generating an input signal by an input signal generating device. The method can also include determining whether an insertion event has occurred based on the generated input signal and causing the headphone to operate in 5 a low power mode responsive to an absence of an insertion event determination after a first period of time. The method can also include causing the headphone to operate in an ultra-low power mode responsive to the absence of an insertion event determination after a second period of time that occurs after the first period of time, the ultra-low power mode having a lower power consumption than the low power mode.