公开(公告)号：US11693658B2

公开(公告)日：2023-07-04

申请号：US17443376

申请日：2021-07-26

申请人： Intel Corporation

发明人： Kevin Nealis ,  Anbang Yao ,  Xiaoming Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20 ,  G06N3/044 ,  G06N3/045

CPC分类号： G06F9/3001 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3893 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20 ,  G06F2207/4824

摘要： One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the ternary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

公开(公告)号：US11669933B2

公开(公告)日：2023-06-06

申请号：US17730364

申请日：2022-04-27

申请人： Intel Corporation

发明人： Naveen K. Mellempudi ,  Dheevatsa Mudigere ,  Dipankar Das ,  Srinivas Sridharan

IPC分类号： G06T1/20 ,  G06F5/01 ,  G06F7/501 ,  G06F7/523 ,  G06F7/544 ,  G06F17/15 ,  G06F17/16 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

CPC分类号： G06T1/20 ,  G06F5/01 ,  G06F7/501 ,  G06F7/523 ,  G06F7/5443 ,  G06F17/153 ,  G06F17/16 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F2207/382 ,  G06F2207/4824

摘要： One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to quantize elements of a floating-point tensor to convert the floating-point tensor into a dynamic fixed-point tensor.

公开(公告)号：US11657253B1

公开(公告)日：2023-05-23

申请号：US17238007

申请日：2021-04-22

申请人： Meta Platforms, Inc.

发明人： Liang Xiong ,  Yan Zhu

IPC分类号： G06N3/04 ,  G06F7/08 ,  G06N3/08 ,  G06N5/022 ,  G06Q30/0242 ,  G06N3/045 ,  G06Q50/00 ,  G06Q10/10

CPC分类号： G06N3/04 ,  G06F7/08 ,  G06N3/045 ,  G06N3/08 ,  G06N5/022 ,  G06Q30/0242 ,  G06F2207/4824 ,  G06Q10/10 ,  G06Q50/01

摘要： For a content item with unknown tasks performed by a viewing user on an online system, the online system predicts a likelihood of interacting with each content item using a prediction model associated with a plurality of tasks. The prediction model comprises a plurality of independent layers, a plurality of shared layers and a plurality of separate layers. Each independent layer is configured to extract features, for each task, that are not shared across the plurality of tasks. The plurality of shared layers are configured to extract common features that are shared across the plurality of tasks. Each separate layer is configured to predict likelihood of the viewing user performing a task associated with the separate layer based on the features extracted from the plurality of independent layers and the plurality of shared layers.

公开(公告)号：US11651231B2

公开(公告)日：2023-05-16

申请号：US16806121

申请日：2020-03-02

申请人： Government of the United States of America, as represented by the Secretary of Commerce

发明人： Brian Douglas Hoskins ,  Mark David Stiles ,  Matthew William Daniels ,  Advait Madhavan ,  Gina Cristina Adam

IPC分类号： G06N3/10 ,  G06N3/063 ,  G06N3/04 ,  G06F17/16

CPC分类号： G06N3/10 ,  G06F17/16 ,  G06N3/04 ,  G06N3/0635 ,  G06F2207/4824

摘要： A quasi-systolic array includes: a primary quasi-systolic processor; an edge row bank and edge column bank of edge quasi-systolic processors; and an interior bank of interior quasi-systolic processors. The primary quasi-systolic processor, edge quasi-systolic processor, and interior quasi-systolic processor independently include a quasi-systolic processor and are disposed and electrically connected in rows and columns in the quasi-systolic array.

公开(公告)号：US20190026076A1

公开(公告)日：2019-01-24

申请号：US16039221

申请日：2018-07-18

申请人： Alibaba Group Holding Limited

发明人： Cong Leng ,  Hao Li ,  Zesheng Dou ,  Shenghuo ZHU ,  Rong JIN

IPC分类号： G06F5/01 ,  G06F5/08 ,  G06F7/556 ,  G06F15/78 ,  G06N3/02

CPC分类号： G06F5/01 ,  G06F5/08 ,  G06F7/5443 ,  G06F7/556 ,  G06F15/78 ,  G06F2207/4824 ,  G06N3/02 ,  G06N3/063 ,  G06N3/08

摘要： A method including receiving, by a processor, a computing instruction for a neural network, wherein the computing instruction for the neural network includes a computing rule for the neural network and a connection weight of the neural network, and the connection weight is a power of 2; and inputting, for a multiplication operation in the computing rule for the neural network, a source operand corresponding to the multiplication operation to a shift register, and performing a shift operation based on a connection weight corresponding to the multiplication operation, wherein the shift register outputs a target result operand as a result of the multiplication operation. The neural network uses a shift operation, and a neural network computing speed is increased.

公开(公告)号：US20180075344A1

公开(公告)日：2018-03-15

申请号：US15675390

申请日：2017-08-11

申请人： SK hynix Inc.

发明人： Kenneth C. MA ,  Dongwook SUH

IPC分类号： G06N3/06 ,  G06N3/04

CPC分类号： G06N3/04 ,  G06F7/026 ,  G06F7/48 ,  G06F2207/4824 ,  G06N3/0454 ,  G06N3/0481 ,  G06N3/049 ,  G06N3/06 ,  G06N3/063 ,  G06N3/084 ,  G06N3/088 ,  G06N5/04 ,  G11C11/54 ,  G11C13/0002

摘要： A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; a weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of Axons, outputs of the memory cells of a same column are connected to one of Neurons; timestamp registers registering timestamps of the Axons and the Neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrix in accordance with the adjusting values.

公开(公告)号：US20180046916A1

公开(公告)日：2018-02-15

申请号：US15458837

申请日：2017-03-14

申请人： NVIDIA Corporation

发明人： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC分类号： G06N3/08 ,  G06F7/523 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06F7/523 ,  G06F7/5443 ,  G06F2207/4824 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/082 ,  G06N3/084

摘要： A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. Compressed-sparse data is received for input to a processing element, wherein the compressed-sparse data encodes non-zero elements and corresponding multi-dimensional positions. The non-zero elements are processed in parallel by the processing element to produce a plurality of result values. The corresponding multi-dimensional positions are processed in parallel by the processing element to produce destination addresses for each result value in the plurality of result values. Each result value is transmitted to a destination accumulator associated with the destination address for the result value.

公开(公告)号：US20180005108A1

公开(公告)日：2018-01-04

申请号：US15199800

申请日：2016-06-30

申请人： HRL LABORATORIES, LLC

发明人： JOSE CRUZ-ALBRECHT ,  TIMOTHY DEROSIER ,  NARAYAN SRINIVASA

IPC分类号： G06N3/063 ,  G06F7/523 ,  G06F7/50

CPC分类号： G06N3/063 ,  G06F7/48 ,  G06F7/50 ,  G06F7/523 ,  G06F2207/4824

摘要： A circuit for emulating the behavior of biological neural circuits, the circuit including a plurality of nodes wherein each node comprises a neuron circuit, a time multiplexed synapse circuit coupled to an input of the neuron circuit, a time multiplexed short term plasticity (STP) circuit coupled to an input of the node and to the synapse circuit, a time multiplexed Spike Timing Dependent Plasticity (STDP) circuit coupled to the input of the node and to the synapse circuit, an output of the node coupled to the neuron circuit; and an interconnect fabric coupled between the plurality of nodes for providing coupling from the output of any node of the plurality of nodes to any input of any other node of the plurality of nodes.

公开(公告)号：US20170330070A1

公开(公告)日：2017-11-16

申请号：US15445906

申请日：2017-02-28

申请人： Purdue Research Foundation

发明人： Abhronil Sengupta ,  Sri Harsha Choday ,  Yusung Kim ,  Kaushik Roy

IPC分类号： G06N3/063 ,  H01L27/22 ,  G06F7/58 ,  G06N3/04 ,  H01L43/08 ,  H01L43/06

CPC分类号： G06N3/0635 ,  G06F7/48 ,  G06F7/588 ,  G06F2207/4824 ,  G06N3/04 ,  G06N3/084 ,  H01L27/228 ,  H01L27/2409 ,  H01L43/06 ,  H01L43/08

摘要： An electronic neuron device that includes a thresholding unit which utilizes current-induced spin-orbit torque (SOT). A two-step switching scheme is implemented with the device. In the first step, a charge current through heavy metal (HM) places the magnetization of a nano-magnet along the hard-axis (i.e. an unstable point for the magnet). In the second step, the device receives a current (from an electronic synapse) which moves the magnetization from the unstable point to one of the two stable states. The polarity of the net synaptic current determines the final orientation of the magnetization. A resistive crossbar array may also be provided which functions as the synapse generating a bipolar current that is a weighted sum of the inputs of the device.

公开(公告)号：US12093808B2

公开(公告)日：2024-09-17

申请号：US17116623

申请日：2020-12-09

申请人： Arm Limited

发明人： Paul Nicholas Whatmough

IPC分类号： G06N3/063 ,  G06F7/544 ,  G06F17/15

CPC分类号： G06N3/063 ,  G06F7/5443 ,  G06F17/15 ,  G06F2207/4824

摘要： An artificial neural network (ANN) accelerator is provided. The ANN accelerator includes digital controlled oscillators (DCOs), digital-to-time converters (DTCs) and a mixed-signal multiply-and-accumulate (MAC) array. Each DCO generates a first analog operand signal based on a first digital data value, and transmits the first analog operand signal along a respective column signal line. Each DTC generates a second analog operand signal based on a second digital data value, and transmits the second analog operand signal along a respective row signal line. The mixed-signal MAC array is coupled to the row and column signal lines, and includes mixed-signal MAC units. Each mixed-signal MAC unit includes an integrated clock gate (ICG) that generates a digital product signal based on the first and second analog operand signals, and a counter circuit that increments or decrements a count value stored in a register based on the digital product signal.