公开(公告)号：US20040105502A1

公开(公告)日：2004-06-03

申请号：US10308593

申请日：2002-12-03

Applicant: M/A-COM, Inc.

Inventor： David Bengtson

IPC: H04L027/00

CPC classification number: H03C3/0991 ,  H03C3/0925 ,  H03C3/0933

Abstract: An apparatus for electromagnetic processing comprises a modulator for generating one or more elements representative of an input signal; a divider controlled by the one or more elements and receiving an electromagnetic wave to generate a modified signal; a comparator for comparing the modified signal to a reference signal and for generating a processed signal based upon the comparison; and a channel number calculator for selecting a channel for the processed signal, wherein the input signal incorporated the channel selection.

Abstract translation: 一种用于电磁处理的装置包括用于产生表示输入信号的一个或多个元件的调制器; 由所述一个或多个元件控制的并且接收电磁波以产生修改信号的分频器; 比较器，用于将修改的信号与参考信号进行比较，并用于基于该比较产生处理的信号; 以及频道号计算器，用于选择处理信号的频道，其中输入信号包含频道选择。

公开(公告)号：US20040036539A1

公开(公告)日：2004-02-26

申请号：US10646175

申请日：2003-08-22

Inventor： Markus Hammes ,  Stefan Van Waasen

IPC: H03L007/00

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/0893 ,  H03L7/1976

Abstract: In the case of a trimming method for a PLL circuit operating based on the principle of a two-point modulation, the PLL circuit is locked without any modulation being impressed and then an analog and a digital modulation signal are impressed into the locked PLL circuit. A signal that is characteristic of the PLL control error is tapped from the PLL circuit, and the modulation swing in the analog modulation signal is changed such that the characteristic signal has the same value as before the analog and digital modulation signals were impressed.

Abstract translation: 在基于两点调制原理操作的PLL电路的修整方法的情况下，PLL电路被锁定，而不施加任何调制，然后将模拟和数字调制信号施加到锁定的PLL电路中。 从PLL电路抽出具有PLL控制误差特性的信号，模拟调制信号中的调制摆幅变化，使得特征信号与模拟和数字调制信号之前的值相同。

公开(公告)号：US06690215B2

公开(公告)日：2004-02-10

申请号：US09942449

申请日：2001-08-29

Applicant: Earl W. McCune, Jr. ,  Wendell B. Sander

Inventor： Earl W. McCune, Jr. ,  Wendell B. Sander

IPC: H03L700

CPC classification number: H03C3/0933 ,  H03C3/0966 ,  H03L7/085 ,  H03L7/0891 ,  H03L7/16 ,  H03L7/1806

Abstract: The present invention, generally speaking, satisfies the foregoing requirements using in combination within a frequency synthesis loop an SDM-based synthesizer and an SDM-based frequency digitizer. Since both blocks are SDM-based, the resulting signals can be differenced and filtered to produce a control signal for an oscillator. Low noise (and low spurs), fine frequency resolution and fast switching times may all be achieved simultaneously.

Abstract translation: 一般而言，本发明在基于SDM的合成器和基于SDM的频率数字化仪的频率合成循环中组合地满足上述要求。 由于两个块都是基于SDM的，所得到的信号可以被差分和滤波，以产生振荡器的控制信号。 低噪声（低杂散），精细的频率分辨率和快速切换时间都可以同时实现。

公开(公告)号：US06681101B1

公开(公告)日：2004-01-20

申请号：US09481094

申请日：2000-01-11

Applicant: Brian Eidson ,  Mats Lindstrom ,  Robert Edmund Grange

Inventor： Brian Eidson ,  Mats Lindstrom ,  Robert Edmund Grange

IPC: H04B104

CPC classification number: H03C3/0933 ,  H03C3/0925 ,  H03C5/00 ,  H03F1/0222 ,  H03G3/004 ,  H04B1/04

Abstract: A highly efficient radio frequency (RF) transmitter provides both wide bandwidth and an extended power control range. The RF transmitter includes stage switching, bias adjustment, and drain supply modulation. These components are used to provide fine and coarse power control and EER envelope fluctuations. The RF transmitter is useful in wireless communications to increase both handset talk time and battery life.

Abstract translation: 高效射频（RF）发射机提供宽带宽和扩展功率控制范围。 RF发射器包括级开关，偏置调节和漏极供应调制。 这些组件用于提供精细和粗略的功率控制和EER包络波动。 RF发射器在无线通信中是有用的，以增加手机通话时间和电池寿命。

公开(公告)号：US20030058055A1

公开(公告)日：2003-03-27

申请号：US09966205

申请日：2001-09-26

Inventor： Kartik Sridharan

IPC: H03B007/12

CPC classification number: H03C3/0933 ,  H03C3/0925 ,  H03L7/1976

Abstract: In a fractional-N frequency synthesizer, a circuit for generating at least one off-axis zero in an equation representative of the circuit.

公开(公告)号：US06392493B1

公开(公告)日：2002-05-21

申请号：US09633763

申请日：2000-08-07

Applicant: Brian J. Minnis

Inventor： Brian J. Minnis

IPC: H03L7197

CPC classification number: H03C3/0933 ,  H03C3/0925 ,  H03L7/197 ,  H04L27/20

Abstract: A fractional-N frequency synthesizer for use in a transmitter for transmitting TDMA signals, comprises a fourth order sigma-delta modulator(16) having an input for digitized signals, a FIR filter(18) having 2 taps coupled to an output of the sigma-delta modulator, the FIR filter (18) serving to increase the number of states on its output by one over the number of states on its input which is connected to an output of the sigma-delta modulator, and a phase locked loop(PLL) including a frequency divider(20) with an incremental ratio of 0.5 and having a control input coupled to an output of the FIR filter. The frequency divider (20) by having an incremental ratio of 0.5 enables the PLL to have a reference oscillator(24) operating at half the sampling frequency of the sigma-delta modulator(16). The frequency synthesizer as a consequence has been found to give a 12 dB improvement in noise level and also continuous tuning can be achieved because the successive groups of three half ratios adjacent tuning ranges made possible by using overlap.

Abstract translation: 一种用于发送TDMA信号的发射机的分数N频率合成器包括具有用于数字化信号的输入的第四级Σ-Δ调制器（16），具有耦合到西格玛输出的2个抽头的FIR滤波器（18） FIR滤波器（18）用于将其输出上的状态数量增加1个，其输入端上的状态数量连接到Σ-Δ调制器的输出，以及锁相环（PLL） ），其包括具有0.5的增量比的分频器（20），并且具有耦合到FIR滤波器的输出的控制输入。 分频器（20）通过具有0.5的增量比使得PLL具有以Σ-Δ调制器（16）的采样频率的一半工作的参考振荡器（24）。 已经发现频率合成器的噪声水平提高了12dB，并且可以实现连续调谐，因为通过使用重叠使相邻调谐范围的三个半比率的连续组成为可能。

公开(公告)号：US06211747B1

公开(公告)日：2001-04-03

申请号：US09322533

申请日：1999-05-28

Applicant: Jacques Trichet ,  Christophe Fourtet

Inventor： Jacques Trichet ,  Christophe Fourtet

IPC: H03C309

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/1974

Abstract: A direct modulation multi-accumulator fractional-N frequency synthesizer 1 for generating a carrier signal 150 modulated by a modulation signal 170, 121 is disclosed. The frequency synthesizer includes a Voltage Controlled Oscillator, VCO 50, having a tuning port for controlling the frequency of the signal 110 output by the VCO, a variable divider 20 and a multi-accumulator sequence generator 21 for controlling the variable divider, a reference signal generator 50, a phase detector 30 and a low pass filter 40. These elements are arranged to form a Phase Locked Loop arrangement, the directly modulated output signal of which is taken from the output of the VCO, wherein in-band modulation is performed by varying the variable divider and out-of-band modulation is performed by directly applying the modulating signal to the VCO tuning port.

Abstract translation: 公开了一种用于产生由调制信号170,121调制的载波信号150的直接调制多分频分数N频率合成器1。 频率合成器包括压控振荡器VCO50，VCO50具有用于控制由VCO输出的信号110的频率的调谐端口，用于控制可变分频器的可变分频器20和多累加器序列发生器21，参考信号 发生器50，相位检测器30和低通滤波器40.这些元件被布置成形成锁相环装置，其直接调制输出信号取自VCO的输出，其中带内调制由 通过将调制信号直接施加到VCO调谐端口来执行改变可变分频器和带外调制。

公开(公告)号：US06181212B2

公开(公告)日：2001-01-30

申请号：US09238990

申请日：1999-01-28

Applicant: Ramin Khoini-Poorfard ,  Hussein K. Mecklai

Inventor： Ramin Khoini-Poorfard ,  Hussein K. Mecklai

IPC: H03L7197

CPC classification number: H03C3/0933 ,  H03C3/40 ,  H03D7/163 ,  H03D7/165 ,  H03L7/1976 ,  H04B1/00 ,  H04B1/28 ,  H04B1/406

Abstract: A method and apparatus for generating two disparate frequency reference signals using a single phase locked loop. The circuit includes a local oscillator for generating a reference signal and a phase comparator for comparing the reference signal with a feedback signal. The output of the phase comparator is converted to a first one of the desired output frequencies by a voltage controlled oscillator. That signal is also fed to a variable frequency divider circuit under control of a &Sgr;/&Dgr; converter which generates a lower frequency signal without creating a secondary frequency tone. The lower frequency signal is the second of the output frequencies. This signal also is fed back to the second input of the phase comparator through a fixed frequency divider.

Abstract translation: 一种用于使用单个锁相环产生两个不同频率参考信号的方法和装置。 电路包括用于产生参考信号的本地振荡器和用于将参考信号与反馈信号进行比较的相位比较器。 相位比较器的输出通过压控振荡器转换成所需输出频率的第一个。 该信号也在SIGMA / DELTA转换器的控制下馈送到可变分频器电路，该转换器产生较低频率信号而不产生辅助频率音调。 低频信号是输出频率的第二个。 该信号也通过固定分频器反馈到相位比较器的第二输入端。

公开(公告)号：US5889443A

公开(公告)日：1999-03-30

申请号：US926756

申请日：1997-09-10

Applicant: Klaus J.o slashed.rgensen

Inventor： Klaus J.o slashed.rgensen

IPC: H03C3/09 ,  H03L7/193 ,  H03L7/197 ,  H04L27/12 ,  H03C3/00

CPC classification number: H03C3/0958 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/193 ,  H03L7/197 ,  H04L27/12

Abstract: A frequency synthesizing circuit has an input on which a bit flow is received, and an output on which a data-modulated output signal is supplied. The circuit moreover comprises a crystal oscillator supplying a reference clock signal, a phase-locked loop (PLL) having a VCO and a phase detector. The phase detector compares the data-modulated output signal with the reference clock signal and, in response to this, supplies an error signal by means of which the VCO output frequency is controlled. A compensation circuit, which receives a measure of the bit flow received, compensates the data-modulated output signal in the phase-locked loop in response to this before it is supplied to the phase detector.

Abstract translation: 频率合成电路具有接收位流的输入和提供数据调制输出信号的输出。 该电路还包括提供参考时钟信号的晶体振荡器，具有VCO的锁相环（PLL）和相位检测器。 相位检测器将数据调制输出信号与参考时钟信号进行比较，并且响应于此，提供控制VCO输出频率的误差信号。 接收到接收到的比特流的量度的补偿电路在被提供给相位检测器之前，根据该补偿电路补偿锁相环中的数据调制输出信号。

公开(公告)号：US5834987A

公开(公告)日：1998-11-10

申请号：US902836

申请日：1997-07-30

Applicant: Paul Wilkinson Dent

Inventor： Paul Wilkinson Dent

IPC: H03C3/09 ,  H03L7/197 ,  H03C3/00 ,  H03C1/00 ,  H03K7/02 ,  H03L7/18

CPC classification number: H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0966 ,  H03L7/1974 ,  H03L7/1976

Abstract: A frequency synthesizer includes a controlled oscillator which is responsive to a frequency control input signal, to generate an output frequency. A programmable frequency divider is responsive to the output frequency and to a divider control input, to divide the output frequency by a first integral ratio or by a second integral ratio in response to the divider control input, to thereby produce a divided signal. A phase comparator is responsive to a reference frequency signal and to the divided signal, to compare the reference frequency signal and the divided signal, and thereby produce a first error signal. A sigma-delta modulator is responsive to a modulation input to produce the divider control input. A loop filter is responsive to the first error signal, to thereby produce the frequency control input signal. Ripple compensation signals and direct modulation signals may also be provided, to provide a three-point modulator for a frequency synthesizer. Analog and digital embodiments may also be provided.

Abstract translation: 频率合成器包括响应于频率控制输入信号的受控振荡器，以产生输出频率。 可编程分频器响应于输出频率和分频器控制输入，以响应于分频器控制输入将输出频率除以第一积分比或第二积分比，从而产生分频信号。 相位比较器响应于参考频率信号和分频信号，以比较参考频率信号和分频信号，从而产生第一误差信号。 Σ-Δ调制器响应于调制输入以产生除法器控制输入。 环路滤波器响应于第一误差信号，从而产生频率控制输入信号。 还可以提供纹波补偿信号和直接调制信号，以提供用于频率合成器的三点调制器。 还可以提供模拟和数字实施例。