公开(公告)号：US06927720B2

公开(公告)日：2005-08-09

申请号：US10948654

申请日：2004-09-24

申请人： Tetsuya Matsumoto

发明人： Tetsuya Matsumoto

IPC分类号： H03M1/66 ,  H03M1/68 ,  H03M3/02 ,  H03M3/04 ,  H03M7/36

CPC分类号： H03M3/344 ,  H03M3/358 ,  H03M3/502 ,  H03M7/3026 ,  H03M7/3031

摘要： An analog signal outputting circuit comprises two unit analog circuits for outputting an analog signal, corresponding to levels “−1” or “1”, and a low-pass filter for smoothing the analog signal output from the two unit analog circuits, as selected by codes output from the four-valued delta-sigma modulator. In case the input signal is −2 or +2, outputs of the unit analog circuits are summed together to output an analog signal corresponding to −2 or +2. In case the input signal is −1 or +1, outputs of the unit analog circuits are alternately used to output an analog signal corresponding to −1 or +1 to reduce the non-linearity error resulting from variations in the analog devices.

公开(公告)号：US06864815B2

公开(公告)日：2005-03-08

申请号：US10886325

申请日：2004-07-07

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03F3/217 ,  H03M3/02 ,  H03M7/32 ,  H03M1/00 ,  H03M3/00

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.In another aspect of the invention, additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

摘要翻译： 描述了一种创建高效数字放大​​器的系统和方法，该数字放大器可以采用模拟或数字输入，并且产生用于驱动扬声器或其他低阻抗负载的输入的高功率精确表示。 一旦检测到输出转换，该系统采用转换检测器和延迟单元，其允许信号调制器的比较器忽略其输入以用于预定数量的后续时钟周期。 通过使用更快的时钟和可变时钟周期跳过比较器的输出转换，实现了用于噪声整形的反馈时钟周期的更好的分辨率。 时钟周期的更好的分辨率允许本发明采用比先前可能的更积极的噪声整形。在本发明的另一方面，通过使用功率输出级的公共桥接实现来获得附加的Δ-Σ调制器噪声抑制， 改进配置桥以创建3状态而不是传统的2状态。 通过彼此独立地控制桥的两半，具有3个状态的输出改善了噪声整形性能。

公开(公告)号：US20040052310A1

公开(公告)日：2004-03-18

申请号：US10629418

申请日：2003-07-29

发明人： Masayoshi Noguchi ,  Gen Ichimura ,  Nobukazu Suzuki

IPC分类号： H04B014/04 ,  H04B014/06

CPC分类号： H03M7/302 ,  H03M7/3026 ,  H03M7/3028 ,  H03M7/3031 ,  H03M7/304

摘要： The present invention relates to a device for performing predetermined processing on a signal inputted thereto that may have signal amplitude of more than one bit, which signal is obtained by subjecting one-bit serial signals to predetermined signal processing, wherein the signal amplitude of more than one bit is converted to a one-bit serial signal by accumulating the signal amplitude exceeding that of one bit, delaying the accumulated signal on the basis of the input signal, and outputting the accumulated signal.

摘要翻译： 本发明涉及一种用于对输入的信号执行预定处理的装置，其可以具有多于一位的信号幅度，该信号是通过使一位串行信号进行预定的信号处理而获得的，其中信号幅度大于 通过累积超过一位的信号幅度将一位转换为1位串行信号，根据输入信号延迟累积信号，并输出累积信号。

公开(公告)号：US20040046680A1

公开(公告)日：2004-03-11

申请号：US10416443

申请日：2003-05-12

发明人： Toshihiko Masuda ,  Kazunobu Ohkuri

IPC分类号： H03M003/00

CPC分类号： H03F3/217 ,  H03F2200/331 ,  H03M3/388 ,  H03M3/506 ,  H03M7/3026 ,  H03M7/3031

摘要： The present invention is directed to a signal amplifier apparatus adapted for carrying out delta-sigma modulation of an input signal to carry out pulse width modulation of that signal S1 to obtain PWM signal S2 to amplify this PWM signal S2 by an amplifier so that a signal S3 of a predetermined magnitude is provided, wherein the signal amplifier apparatus comprises a correction circuit (104) for correcting output of a quantizer (103) provided at a delta-sigma modulation device (10), and the correction circuit (104) is installed (provided) at feedback path with respect to the input side from the quantizer (103) or immediately before a pulse width modulator (11) to thereby correct distortion taking place at the amplifier. In addition, the signal amplifier apparatus according to the present invention compares PWM signals at input and output of the amplifier to correct output of the quantizer (103) provided at the delta-sigma modulation device (10) so as to cancel distortion quantity taking place at the amplifier in accordance with respective rising time difference and falling time difference to thereby correct distortion taking place at the amplifier.

摘要翻译： 本发明涉及一种信号放大器装置，适用于对输入信号进行Δ-Σ调制，以执行该信号S1的脉冲宽度调制以获得PWM信号S2，以通过放大器放大该PWM信号S2，使得信号 提供预定幅度的S3，其中信号放大器装置包括用于校正设置在Δ-Σ调制装置（10）处的量化器（103）的输出的校正电路（104），并且校正电路（104）被安装 （提供）在反馈路径上相对于来自量化器（103）的输入侧或紧接在脉冲宽度调制器（11）之前，从而校正在放大器处发生的失真。 此外，根据本发明的信号放大装置比较放大器输入和输出端的PWM信号，以校正设在Δ-Σ调制装置（10）的量化器（103）的输出，以消除发生的失真量 根据相应的上升时间差和下降时间差在放大器处，从而校正在放大器处发生的失真。

公开(公告)号：US06496127B2

公开(公告)日：2002-12-17

申请号：US09768674

申请日：2001-01-24

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03M106

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible. In another aspect of the invention, additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

摘要翻译： 描述了一种创建高效数字放大​​器的系统和方法，该数字放大器可以采用模拟或数字输入，并且产生用于驱动扬声器或其他低阻抗负载的输入的高功率精确表示。 一旦检测到输出转换，该系统采用转换检测器和延迟单元，其允许信号调制器的比较器忽略其输入以用于预定数量的后续时钟周期。 通过使用更快的时钟和可变时钟周期跳过比较器的输出转换，实现了用于噪声整形的反馈时钟周期的更好的分辨率。 时钟周期的更好的分辨率允许本发明采用比先前可能的更积极的噪声整形。在本发明的另一方面，通过使用功率输出级的公共桥接实现来获得附加的Δ-Σ调制器噪声抑制， 改进配置桥以创建3状态而不是传统的2状态。 通过彼此独立地控制桥的两半，具有3个状态的输出改善了噪声整形性能。

公开(公告)号：US20020186155A1

公开(公告)日：2002-12-12

申请号：US10214239

申请日：2002-08-07

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03M003/00

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible. In another aspect of the invention, additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

摘要翻译： 描述了一种创建高效数字放大​​器的系统和方法，该数字放大器可以采用模拟或数字输入，并且产生用于驱动扬声器或其他低阻抗负载的输入的高功率精确表示。 一旦检测到输出转换，该系统采用转换检测器和延迟单元，其允许信号调制器的比较器忽略其输入以用于预定数量的后续时钟周期。 通过使用更快的时钟和可变时钟周期跳过比较器的输出转换，实现了用于噪声整形的反馈时钟周期的更好的分辨率。 时钟周期的更好的分辨率允许本发明采用比先前可能的更积极的噪声整形。 在本发明的另一方面，通过使用功率输出级的共同桥接实现，通过改进配置桥以创建3态条件而不是传统的2状态来获得附加的Δ-Σ调制器噪声抑制。 通过彼此独立地控制桥的两半，具有3个状态的输出改善了噪声整形性能。

公开(公告)号：US06292122B1

公开(公告)日：2001-09-18

申请号：US09517766

申请日：2000-03-04

申请人： Saed Younis ,  Emilija Simic ,  Thomas Wilborn

发明人： Saed Younis ,  Emilija Simic ,  Thomas Wilborn

IPC分类号： H03M300

CPC分类号： H03F3/24 ,  H03F2200/331 ,  H03G3/3036 ,  H03M3/374 ,  H03M3/50 ,  H03M7/3031

摘要： An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and generates an adjusted signal. The modulator couples to the time response adjustment circuit, receives the adjusted signal, and generates a modulator signal. The filter couples to the modulator, receives the modulator signal, and generates the analog signal. The analog signal has a time response that is modified by the time response adjustment circuit. In an embodiment, the time response adjustment circuit includes a gain element, a delay element, and a summer. The gain element receives and scales the digital signal by a scaling factor. The delay element receives and delays the digital signal by a time delay. The summer couples to the gain element and the delay element, sums the scaled signal from the gain element and the delayed signal from the delay element to generate the adjusted signal.

摘要翻译： 一种用于将数字信号转换为模拟信号的接口电路。 接口电路包括时间响应调整电路，调制器和滤波器。 时间响应调整电路接收数字信号并产生调整信号。 调制器耦合到时间响应调整电路，接收经调整的信号，并产生调制器信号。 滤波器耦合到调制器，接收调制器信号，并产生模拟信号。 模拟信号具有由时间响应调整电路修改的时间响应。 在一个实施例中，时间响应调整电路包括增益元件，延迟元件和加法器。 增益元件以缩放因子接收和缩放数字信号。 延迟元件接收并延迟数字信号延时。 加法器与增益元件和延迟元件耦合，将来自增益元件的定标信号和来自延迟元件的延迟信号相加，以产生调整后的信号。