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公开(公告)号：US3198958A
公开(公告)日：1965-08-03
申请号：US13385761
申请日：1961-08-25
申请人： BUNKER RAMO
发明人： SAMUEL NISSIM
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56.发明授权Dynamic storage circuit utilizing two tunnel diodes and reflective delay line 失效动态存储电路利用两个隧道二极管和反射延迟线
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公开(公告)号：US3107345A
公开(公告)日：1963-10-15
申请号：US6073260
申请日：1960-10-05
申请人： IBM
发明人： GRUODIS ALGIRDAS J
IPC分类号： G11C11/38
CPC分类号： G11C11/38
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公开(公告)号：US3040304A
公开(公告)日：1962-06-19
申请号：US84286659
申请日：1959-09-28
IPC分类号： C04B2/06 , C04B22/00 , G11C7/02 , G11C11/38 , H03B19/03 , H03K3/45 , H03K17/58 , H03K17/82 , H03K25/00 , H03M1/00 , H04B14/04
CPC分类号： C04B2/06 , C04B22/0086 , G11C11/38 , H03B19/03 , H03K3/45 , H03K17/58 , H03K17/82 , H03K25/00 , H03M1/00 , H03M1/1009 , H04B14/044
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公开(公告)号：US20240334672A1
公开(公告)日：2024-10-03
申请号：US18194795
申请日：2023-04-03
发明人： Jenn-Gwo HWU , Sung-Wei HUANG
CPC分类号： H10B12/01 , G11C11/38 , G11C11/5628 , G11C11/5642 , H01L29/0626 , H01L29/66151
摘要： A method includes forming a metal-insulator-semiconductor (MIS) structure, in which the MIS structure includes a semiconductor layer, an insulating layer over the semiconductor layer, and a metal electrode layer over the insulating layer; performing a soft breakdown process to the MIS structure to form a local breakdown portion in the insulating layer; performing a first write operation by supplying a first voltage pulse; performing a first read operation by supplying a second voltage pulse and detecting a first read current flowing through the MIS structure; performing a second write operation by supplying a third voltage pulse, in which the first voltage pulse has a higher voltage level than the third voltage pulse; and performing a second read operation by supplying a fourth voltage pulse and detecting a second read current flowing through the MIS structure, in which the first read current is different from the second read current.
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公开(公告)号：US11855099B2
公开(公告)日：2023-12-26
申请号：US17582674
申请日：2022-01-24
发明人： Jenn-Gwo Hwu , Ting-Hao Hsu
IPC分类号： H01L29/88 , H01L27/105 , G11C11/38 , H01L27/102 , H01L29/66 , H10B99/00
CPC分类号： H01L27/1021 , H01L27/105 , H01L29/66151 , H01L29/88 , H10B99/16 , G11C11/38
摘要： A method includes forming a first dielectric layer over the substrate and covering first, second, third, fourth, fifth and sixth protrusion regions; forming first, second, and third gate conductors over the first, fourth, and fifth protrusion regions, respectively; performing a first implantation process to form a second source region and a second drain region in the fourth protrusion region; performing a second implantation process to form a first source region and a first drain region in the first protrusion region, and to form a third source region and a third drain region in the fifth protrusion region; forming a metal layer over the third protrusion region; patterning the metal layer to form an inner circular electrode and an outer ring electrode encircling the inner circular electrode; forming a word line; and forming a bit line.
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