公开(公告)号：US11106576B2

公开(公告)日：2021-08-31

申请号：US16781510

申请日：2020-02-04

申请人： Samsung Electronics Co., Ltd.

发明人： Sangwoo Lim ,  Dongkun Shin

IPC分类号： G06F12/02 ,  G06F11/34 ,  G06K9/62 ,  G06F12/0873 ,  G06F12/123 ,  G06F13/16 ,  G06F11/30

摘要： There is provided a data storage device for managing memory resources by using a flash translation layer (FTL) for condensing mapping information. The FTL divides a total logical address space for input and output requests of a host into n virtual logical address streams, generates a preliminary cluster mapping table in accordance with stream attributes of the n virtual logical address streams, generates a condensed cluster mapping table by performing a k-mean clustering algorithm on the preliminary cluster mapping table, and generates a cache cluster mapping table configured as a part of a condensed cluster mapping table frequently referred to by using a DFTL method. The FTL extends a space of data buffers allotted to non-mapped physical address streams to a DFTL cache map in a data buffer of a volatile memory device by the condensed cluster mapping table.

公开(公告)号：US20210263852A1

公开(公告)日：2021-08-26

申请号：US16939845

申请日：2020-07-27

申请人： SK hynix Inc.

发明人： Ji Hoon SEOK

IPC分类号： G06F12/0873 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/02

摘要： A computing system includes a host and a storage device. The host includes a host memory, and the storage device includes a processor, a semiconductor memory device and a device memory which caches mapping information of the semiconductor memory device. In operation, the processor transmits to the host read data and mapping table entry information of a logical address region corresponding to the read data in response to a read request. The mapping table entry information is transmitted to the host based on features of the logical address region. Additionally, the host may transmit a read buffer request corresponding to the mapping table entry information to the storage device, and the storage device may transmit mapping information corresponding to the read buffer request to the host, which then stores the mapping information in the host memory.

公开(公告)号：US11086783B2

公开(公告)日：2021-08-10

申请号：US16598569

申请日：2019-10-10

申请人： International Business Machines Corporation

发明人： Koichi Masuda ,  Katja I. Denefleh ,  Joseph M. Swingler

IPC分类号： G06F12/0871 ,  G06F3/06 ,  G06F12/0873

摘要： A dynamic premigration protocol is implemented in response to a secondary tier returning to an operational state and an amount of data associated with a premigration queue of a primary tier exceeding a first threshold. The dynamic premigration protocol can comprise at least a temporary premigration throttling level. An original premigration protocol is implemented in response to an amount of data associated with the premigration queue decreasing below the first threshold.

公开(公告)号：US20210240629A1

公开(公告)日：2021-08-05

申请号：US16782316

申请日：2020-02-05

申请人： Arm Limited

发明人： Tessil THOMAS ,  Jan-Peter LARSSON

IPC分类号： G06F12/0891 ,  G06F12/0882 ,  G06F12/109 ,  G06F7/58 ,  G06F12/1027 ,  G06F11/07 ,  H04L9/08 ,  G06F12/1081 ,  G06F11/30 ,  G06F12/0873 ,  H04L9/06 ,  H04L9/32

摘要： An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.

公开(公告)号：US11074186B1

公开(公告)日：2021-07-27

申请号：US16742739

申请日：2020-01-14

申请人： International Business Machines Corporation

发明人： Ganesh Govindrao Chaudhari ,  Kushal Patel ,  Sachin Chandrakant Punadikar ,  Sarvesh S. Patel

IPC分类号： G06F12/0871 ,  G06F12/0811 ,  G06F1/30 ,  G06F11/30 ,  G06F12/0873

摘要： A computer-implemented method according to one embodiment includes managing a cache in a tiered data storage system. The cache is configured to be powered by a temporary power source during a power loss event. The managing includes determining an amount of time that the temporary power source is capable of powering the cache before the temporary power source is depleted, and maintaining a dynamic cache size. The maintaining includes dynamically selecting the cache size based on the amount of time that the temporary power source is capable of powering the cache before the temporary power source is depleted, and based on a latency of destaging extents of data in the cache.

公开(公告)号：US20210149595A1

公开(公告)日：2021-05-20

申请号：US16688250

申请日：2019-11-19

申请人： Micron Technology, Inc.

发明人： Shivasankar Gunasekaran ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel

IPC分类号： G06F3/06 ,  G06F11/07 ,  G06F12/0873

摘要： A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory subsystem can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.

公开(公告)号：US11010301B2

公开(公告)日：2021-05-18

申请号：US16572929

申请日：2019-09-17

申请人： EMC IP Holding Company LLC

发明人： Ruiyong Jia ,  Xinlei Xu ,  Lifeng Yang ,  Yousheng Liu ,  Changyu Feng

IPC分类号： G06F12/0873 ,  G06F12/1045 ,  G06F12/0891

摘要： Techniques provide cache service in a storage system. Such techniques involve a storage cell pool, a cache and an underlying storage system. The storage cell pool includes multiple storage cells, a storage cell among the multiple storage cells being mapped to a physical address in the underlying storage system via an address mapping of the storage system. Specifically, an access request for target data at a virtual address in the storage cell pool is received, and the type of the access request is determined. The access request is served with the cache on the basis of the determined type, where the cache is used to cache data according to a format of a storage cell in the storage cell pool. The cache directly stores data in various storage cells in the pool that is visible to users, so that response speed for the access request may be increased.

公开(公告)号：US10997081B2

公开(公告)日：2021-05-04

申请号：US16425455

申请日：2019-05-29

申请人： Western Digital Technologies, Inc.

发明人： Ramanathan Muthiah ,  Ramkumar Ramamurthy

IPC分类号： G06F9/345 ,  G06F12/0873 ,  G06F12/12 ,  G06F12/10

摘要： A storage system, host, and method for storage system calibration are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: determine a pattern of host writes to the memory; determine whether the pattern of host writes matches a granularity of a logical-to-physical address map used by the storage system; and in response to determining that the pattern of host writes does not match the granularity of the logical-to-physical address map used by the storage system, change the granularity of the logical-to-physical address map used by the storage system. In another embodiment, the storage system calibration is done by host directive. Other embodiments are provided.

公开(公告)号：US20210064521A1

公开(公告)日：2021-03-04

申请号：US16821789

申请日：2020-03-17

申请人： SK hynix Inc.

发明人： Young Ick Cho ,  Sung Kwan Hong ,  Byeong Gyu Park ,  Sung Hun Jeon

IPC分类号： G06F12/02 ,  G06F12/0873 ,  G06F12/0871 ,  G06F12/0804

摘要： A data storage device includes a memory array including a plurality of memory cells; and a controller in communication with the memory array and configured to: store, in a map update buffer, one or more map segments including one or more logical address to be unmapped; determine, among logical address to physical address (L2P) entries of the one or more map segments stored in the map update buffer, L2P entries having the same memory block number; and selectively perform a first unmap operation or a second unmap operation according to whether all the L2P entries stored in the map update buffer have the same memory block number.

公开(公告)号：US20210056026A1

公开(公告)日：2021-02-25

申请号：US16845919

申请日：2020-04-10

申请人： SK hynix Inc.

发明人： Seok-Jun LEE

IPC分类号： G06F12/0811 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0873 ,  G06F12/02 ,  G06F12/14 ,  G06F9/4401 ,  G06F13/16

摘要： A memory system may include: a non-volatile memory device suitable for storing firmware; a volatile memory device comprising a write cache region for temporarily storing write data to be programmed into the non-volatile memory device and a firmware cache region for loading the firmware from the non-volatile memory device; and a controller suitable for: moving, to the write cache region, changeable firmware data that is generated or modified in the firmware cache region during an operation of the controller; programming the changeable firmware data, after it is moved into the write cache region, into the non-volatile memory device; and generating, in the firmware cache region, access information of the changeable firmware data.