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公开(公告)号：US10649514B2
公开(公告)日：2020-05-12
申请号：US15274697
申请日：2016-09-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Wei Huang , Yazhou Zu , Indrani Paul
Abstract: A method and apparatus for managing processing power determine a supply voltage to supply to a processing unit, such as a central processing unit (CPU) or graphics processing unit (GPU), based on temperature inversion based voltage, frequency, temperature (VFT) data. The temperature inversion based VFT data includes supply voltages and corresponding operating temperatures that cause the processing unit's transistors to operate in a temperature inversion region. In one example, the temperature inversion based VFT data includes lower supply voltages and corresponding higher temperatures in a temperature inversion region of a processing unit. The temperature inversion based VFT data is based on an operating frequency of the processing unit. The apparatus and method adjust a supply voltage to the processing unit based on the temperature inversion based VFT data.
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公开(公告)号：US20200133868A1
公开(公告)日：2020-04-30
申请号：US16176466
申请日：2018-10-31
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Maxim V. KAZAKOV
IPC: G06F12/0875 , G06F17/16 , G06F13/16
Abstract: A processor reduces bus bandwidth consumption by employing a shared load scheme, whereby each shared load retrieves data for multiple compute units (CUs) of a processor. Each CU in a specified group monitors a bus for load accesses directed to a cache shared by the multiple CUs. In response to identifying a load access on the bus, a CU determines if the load access is a shared load access for its share group. In response to identifying a shared load access for its share group, the CU allocates an entry of a private cache associated with the CU for data responsive to the shared load access. The CU then monitors the bus for the data targeted by the shared load. In response to identifying the targeted data on the bus, the CU stores the data at the allocated entry of the private cache.
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公开(公告)号：US10606740B2
公开(公告)日：2020-03-31
申请号：US15607118
申请日：2017-05-26
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Yunpeng Zhu , Jimshed Mirza
IPC: G06F12/02 , G06F9/38 , G06F9/48 , G06T1/60 , G06T15/00 , G06F12/0811 , G06F9/30 , G06F12/084
Abstract: Systems, apparatuses, and methods for generating flexibly addressed memory requests are disclosed. In one embodiment, a system includes a processor, control unit, and memory subsystem. The processor launches a plurality of threads on a plurality of compute units, wherein each thread generates memory requests without specifying target memory addresses. The threads executing on the plurality of compute units convey a plurality of memory requests to the control unit. The control unit generates target memory addresses for the plurality of received memory requests. In one embodiment, the memory requests are write requests, and the control unit interleaves write requests from the plurality of threads into a single output buffer stored in the memory subsystem. The control unit can be located in a cache, in a memory controller, or in another location within the system.
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公开(公告)号：US10606599B2
公开(公告)日：2020-03-31
申请号：US15374727
申请日：2016-12-09
Applicant: Advanced Micro Devices, Inc.
Inventor： David N. Suggs
IPC: G06F9/38 , G06F12/0875 , G06F12/0855 , G06F12/0862 , G06F9/30
Abstract: A system and method for using an operation (op) cache is disclosed. The system and method include an op cache for caching previously decoded instructions. The op cache includes a plurality of physically indexed and tagged instructions allowing sharing of instructions between threads. The op cache is chained through multiple ways allowing service of a plurality of instructions in a cache line. The op cache is stored between a shared operation storage and immediate/displacement storage to maximize capacity.
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公开(公告)号：US20200099993A1
公开(公告)日：2020-03-26
申请号：US16138117
申请日：2018-09-21
Applicant: Advanced Micro Devices, Inc.
IPC: H04N21/6405 , H04L12/18 , H04L29/06 , H04N19/164 , H04N19/169
Abstract: Systems, apparatuses, and methods for processing multi-cast messages are disclosed. A system includes at least one or more processing units, one or more memory controllers, and a communication fabric coupled to the processing unit(s) and the memory controller(s). The communication fabric includes a plurality of crossbars which connect various agents within the system. When a multi-cast message is received by a crossbar, the crossbar extracts a message type indicator and a recipient type indicator from the message. The crossbar uses the message type indicator to determine which set of masks to lookup using the recipient type indicator. Then, the crossbar determines which one or more masks to extract from the selected set of masks based on values of the recipient type indicator. The crossbar combines the one or more masks with a multi-cast route to create a port vector for determining on which ports to forward the multi-cast message.
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Patent Agency Ranking
公开(公告)号：US20200089498A1
公开(公告)日：2020-03-19
申请号：US16134440
申请日：2018-09-18
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Arunachalam ANNAMALAI , Marius EVERS , Aparna THYAGARAJAN
Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.
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公开(公告)号：US20200089301A1
公开(公告)日：2020-03-19
申请号：US16133390
申请日：2018-09-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Jyoti Raheja , Alexander J. Branover
IPC: G06F1/32 , G06F9/54 , G06F9/4401
Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.
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公开(公告)号：US10593391B2
公开(公告)日：2020-03-17
申请号：US16038738
申请日：2018-07-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Liang Zhao , YuBin Yao
IPC: G11C11/406 , G06F13/18 , G06F13/16 , G11C11/4076
Abstract: In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator.
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公开(公告)号：US10592207B2
公开(公告)日：2020-03-17
申请号：US16378055
申请日：2019-04-08
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Greg Sadowski , Wayne Burleson
Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.
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公开(公告)号：US20200081651A1
公开(公告)日：2020-03-12
申请号：US16123837
申请日：2018-09-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Shaizeen Aga , Nuwan Jayasena
Abstract: Methods, systems, and devices for near-memory data-dependent gathering and packing of data stored in a memory. A processing device extracts a function, a memory source address, and a memory destination address from a near-memory data-dependent gathering and packing primitive. A signal to perform gathering and packing operations based on the primitive is sent to near-memory processing circuitry of a memory device. The near-memory processing circuitry receives the signal, gathers data from the memory device based on the function and the memory source address, and packs the gathered data into the memory device based on the memory destination address.
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