公开(公告)号：US10759168B2

公开(公告)日：2020-09-01

申请号：US16357077

申请日：2019-03-18

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Simon Dodd ,  David S. Hunt ,  Joseph Edward Scheffelin ,  Dana Gruenbacher ,  Stefan H. Hollinger ,  Uwe Schober ,  Peter Janouch

IPC: B41J2/14 ,  B41J2/175

Abstract: The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support with respect to a direction of ejection of the nozzles, and a semi-flexible support or semi-rigid support that allow the electrical contacts to be moved with respect to a direction of ejection of the nozzles. The semi-flexible and semi-rigid supports allow the die to be up to and beyond a 90 degree angle with respect to a plane of the electrical contacts. The different supports allow for a variety of positions of the microfluidic die with respect to a position of the electrical contacts.

公开(公告)号：US10747282B2

公开(公告)日：2020-08-18

申请号：US16162543

申请日：2018-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla ,  Sandip Atal

IPC: G06F1/24 ,  H03K19/00 ,  G01R31/319 ,  G06F1/3206 ,  H03K17/22

Abstract: An electronic device includes a power management circuit generating output for a plurality of voltage monitors that each detect whether voltages received from a test apparatus are at least a different minimum threshold. The power management circuit also generates a test enable signal indicative of whether the test apparatus is supplying the minimum required voltages to the electronic device. A control circuit receives the output for the plurality of voltage monitors and the test enable signal and generates at least one control signal as a function of the output for the plurality of voltage monitors and the test enable signal. An output circuit receives the at least one control signal and generates an interface control signal that selectively enables or disables interface with analog intellectual property packages within the electronic device, in response to the at least one control signal.

公开(公告)号：US20200235659A1

公开(公告)日：2020-07-23

申请号：US16715209

申请日：2019-12-16

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Shivam KALLA

IPC: H02M3/07 ,  G11C5/14 ,  G11C16/30

Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.

公开(公告)号：US20200183439A1

公开(公告)日：2020-06-11

申请号：US16694028

申请日：2019-11-25

Applicant: STMicroelectronics International N.V.

Inventor： Ankit GUPTA ,  Nitin GUPTA ,  Prashutosh GUPTA

IPC: G05F3/26 ,  G05F1/575

Abstract: A voltage regulator includes an error amplifier producing an error voltage from a reference voltage and a feedback voltage. A voltage-to-current converter converts the error voltage to an output current, and a feedback resistance generates the feedback voltage from the output current. The error amplifier includes a differential pair of transistors receiving the feedback voltage and the reference voltage, a first pair of transistors operating in saturation and coupled to the differential pair of transistors at an output node and a bias node, a second pair of transistors operating in a linear region and coupled to the first pair of transistors at a pair of intermediate nodes. A compensation capacitor is coupled to one of the pair of intermediate nodes so as to compensate the error amplifier for a parasitic capacitance. An output at the output node is a function of a difference between the reference voltage and feedback voltage.

公开(公告)号：US10608637B2

公开(公告)日：2020-03-31

申请号：US15698022

申请日：2017-09-07

Applicant: STMicroelectronics International N.V.

Inventor： Prashant Singh ,  Pratap Narayan Singh

IPC: H03K5/22 ,  H03K5/153 ,  H03K19/003 ,  H03K17/14 ,  H03K19/1778

Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.

公开(公告)号：US20200076437A1

公开(公告)日：2020-03-05

申请号：US16674207

申请日：2019-11-05

Applicant: STMicroelectronics International N.V.

Inventor： Anand KUMAR ,  Nitin GUPTA ,  Nitin JAIN

IPC: H03L1/00 ,  H03L7/183 ,  H03L7/087

Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

公开(公告)号：US20200075090A1

公开(公告)日：2020-03-05

申请号：US16542432

申请日：2019-08-16

Applicant: STMicroelectronics International N.V.

Inventor： Ashish KUMAR ,  Mohammad Aftab ALAM

IPC: G11C11/418 ,  G11C8/08 ,  G11C11/419

Abstract: A wordline coupled to a memory cell is selected in connection with performing a read/write operation at the memory cell. A wordline signal is asserted on the selected wordline. The assertion of the wordline signal has a leading edge and a trailing edge and, between the leading edge and trailing edge, a series of wordline underdrive pulses. Each wordline underdrive pulse causes a wordline voltage to fall from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level. The first and second voltage levels are both greater than a ground voltage of the memory cell.

公开(公告)号：US20200064405A1

公开(公告)日：2020-02-27

申请号：US16671933

申请日：2019-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Manish SHARMA

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3183 ,  G06F11/27 ,  G06F11/267

Abstract: A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.

公开(公告)号：US10543504B2

公开(公告)日：2020-01-28

申请号：US15636491

申请日：2017-06-28

Applicant: STMicroelectronics, Inc. ,  STMICROELECTRONICS S.R.L. ,  STMicroelectronics International N.V.

Inventor： Simon Dodd ,  Joe Scheffelin ,  Dave Hunt ,  Matt Giere ,  Dana Gruenbacher ,  Faiz Sherman

IPC: B05B17/06 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  B41J2/14 ,  B05B17/00 ,  B41J2/175 ,  B41J2/16

Abstract: A microfluidic die is disclosed that includes a plurality of heaters above a substrate, a plurality of chambers and nozzles above the heaters, a plurality of first contacts coupled to the heaters, and a plurality of second contacts coupled to the heaters. The plurality of second contacts are coupled to each other and coupled to ground. The die includes a plurality of contact pads, a first signal line coupled to the plurality of second contacts and to a first one of the plurality of contact pads, and a plurality of second signal lines, each second signal line being coupled to one of the plurality of first contacts, groups of the second signal lines being coupled together to drive a group of the plurality of heaters with a single signal, each group of the second signal lines being coupled to a remaining one of the plurality of contact pads.

公开(公告)号：US10535416B2

公开(公告)日：2020-01-14

申请号：US15723913

申请日：2017-10-03

Applicant: STMicroelectronics International N.V.

Inventor： Nishu Kohli

IPC: G11C29/10 ,  G11C29/24 ,  G11C29/00 ,  G11C29/14 ,  G11C29/54 ,  G11C29/52 ,  G11C29/50 ,  G11C29/56 ,  G11C11/34 ,  G11C11/22 ,  G01R31/3183 ,  G11C11/4063

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.