公开(公告)号：US20060158378A1

公开(公告)日：2006-07-20

申请号：US11281744

申请日：2005-11-17

Applicant: Michel Pons ,  Frederic Lemaire

Inventor： Michel Pons ,  Frederic Lemaire

IPC: H01Q1/38

CPC classification number: H01Q1/52 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q9/285 ,  H01Q15/0013 ,  H01Q23/00

Abstract: The method is to fabricate a microelectronic device with an integrated antenna. This method may include forming at least a first semiconducting layer on a substrate, forming in at least one zone of the first semiconducting layer of a structure to limit the circulation of current in the zone of the first semiconducting layer, forming a plurality of layers on the semiconducting layer and at least one antenna in the plurality of layers, with the antenna being formed opposite the zone. The antenna may be operable at radio frequencies above 10 GHz, and may have an improved emission efficiency.

Abstract translation: 该方法是制造具有集成天线的微电子器件。 该方法可以包括在衬底上形成至少第一半导体层，在结构的第一半导体层的至少一个区域中形成以限制第一半导体层的区域中的电流的循环，从而在第 所述半导体层和所述多个层中的至少一个天线，所述天线与所述区域相对地形成。 天线可以在高于10GHz的无线电频率下操作，并且可以具有改善的发射效率。

公开(公告)号：US20060157699A1

公开(公告)日：2006-07-20

申请号：US11302409

申请日：2005-12-12

Applicant: Michel Vallet ,  Philippe Sardin ,  Thierry Parrassin ,  Sylvain Dudit

Inventor： Michel Vallet ,  Philippe Sardin ,  Thierry Parrassin ,  Sylvain Dudit

IPC: H01L23/58

CPC classification number: G01R31/311 ,  G02B6/00 ,  G02B6/42 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test structure for integrated electronic circuits having a substantially planar substrate coated with a plurality of metallization layers comprises a switching element formed on the surface of the substrate. It also comprises a tunnel formed in one or more metallization layers between the top of the switching element and the front side of the integrated circuit. This tunnel is designed to channel photons emitted by the switching element towards the front side.

Abstract translation: 具有涂覆有多个金属化层的基本平坦的基板的集成电子电路的测试结构包括形成在基板的表面上的开关元件。 它还包括在开关元件的顶部和集成电路的前侧之间的一个或多个金属化层中形成的隧道。 该隧道被设计成将由开关元件发射的光子向前侧传播。

公开(公告)号：US20060134903A1

公开(公告)日：2006-06-22

申请号：US11315447

申请日：2005-12-21

Applicant: Mohamed Boufnichel ,  Patrick Hougron ,  Vincent Jarry

Inventor： Mohamed Boufnichel ,  Patrick Hougron ,  Vincent Jarry

IPC: H01L21/44 ,  B23K31/02

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/0401

Abstract: Forming conductive bumps on an integrated circuit wafer by sucking in conductive balls into cavities of a mask, placing the mask supporting the balls on the integrated circuit wafer, temporarily attaching the mask and the wafer together, cutting the suction, and submitting the mask and wafer assembly to a thermal ball melting processing.

Abstract translation: 在集成电路晶片上形成导电凸块，通过将导电球吸入掩模的空腔中，将支撑球的掩模放置在集成电路晶片上，将掩模和晶片临时附接在一起，切割吸力并提交掩模和晶片 组装到热球熔化处理。

公开(公告)号：US20060133161A1

公开(公告)日：2006-06-22

申请号：US11274039

申请日：2005-11-14

Applicant: Francois Jacquet ,  Florent Vautrin

Inventor： Francois Jacquet ,  Florent Vautrin

IPC: G11C5/14 ,  G11C17/00 ,  G11C11/00

CPC classification number: G11C11/417

Abstract: A memory circuit includes a plurality of storage cells (100) arranged in rows and columns thus forming a storage matrix. The storage cells (100) corresponding to the same bit line (21-23) are divided into several groups (60-61) of cells for the same column, these groups having their own biasing circuit (200) in order to act on the difference between the logic level low voltage and the substrate voltage of the link transistors. When a storage cell is not selected, the biasing circuit makes the voltage between source/drain and substrate equal to a negative voltage in order to minimize the leakage current. During a read operation, the substrate voltage and the source/drain voltage are brought back to the same level such that a maximum current will flow when the link transistor is conducting.

Abstract translation: 存储电路包括以行和列排列的多个存储单元（100），从而形成存储矩阵。 对应于相同位线（21-23）的存储单元（100）被划分成用于同一列的单元的几组（60-61），这些组具有它们自己的偏置电路（200），以便作用于 逻辑电平低电压与链路晶体管的衬底电压之间的差异。 当不选择存储单元时，偏置电路使得源极/漏极和衬底之间的电压等于负电压，以便使漏电流最小化。 在读取操作期间，衬底电压和源极/漏极电压恢复到相同的电平，使得当链路晶体管导通时最大电流将流动。

公开(公告)号：US07061697B2

公开(公告)日：2006-06-13

申请号：US10895012

申请日：2004-07-19

Applicant: Pierangelo Magni ,  Remi Brechignac ,  Chek Lim Kho ,  Kum Weng Loo

Inventor： Pierangelo Magni ,  Remi Brechignac ,  Chek Lim Kho ,  Kum Weng Loo

IPC: G02B7/02 ,  H01J40/14 ,  H01L27/00 ,  H01L21/00

CPC classification number: G02B13/001 ,  G02B7/02 ,  G02B27/62 ,  H01L2224/48227 ,  H04N5/2254

Abstract: A method is described for fixing a lens of an optical group with respect to an optical sensor in an image acquisition device comprising the steps of housing the optical sensor in a housing, fixing a lower holder of the optical group to the housing, aligning an upper holder of the optical group, wherein the lens is placed, with the sensor so as to align a focusing point of the lens with respect to the sensor, welding the upper holder to the lower holder. The welding step may be performed by means of ultrasounds.

Abstract translation: 描述了一种用于在图像采集装置中固定相对于光学传感器的光学组的透镜的方法，包括以下步骤：将光学传感器容纳在壳体中，将光学组的下部固定器固定到壳体上， 将光学组的保持器放置在传感器上，以便使透镜的聚焦点相对于传感器对准，将上支架焊接到下支架。 焊接步骤可以通过超声波进行。

公开(公告)号：US20060115003A1

公开(公告)日：2006-06-01

申请号：US11267949

申请日：2005-11-04

Applicant: Ahmed Kari ,  David Naura

Inventor： Ahmed Kari ,  David Naura

IPC: H04B14/04

CPC classification number: H04L25/4904 ,  G06K7/0008 ,  H03K5/1534

Abstract: A method is provided for decoding an encoded binary data signal and generating a clock signal that is synchronous with the encoded data signal. There is generated, from the encoded data signal, an edge detection signal comprising four pulses per binary state of the encoded data signal. The encoded data signal is sampled every four pulses of the edge detection signal so as to obtain a binary signal of decoded data, and from the edge detection signal there is generated a binary clock signal that is synchronous with the encoded data signal and changes logic state every two pulses of the edge detection signal.

公开(公告)号：US07053754B2

公开(公告)日：2006-05-30

申请号：US10453454

申请日：2003-06-03

Applicant: Christophe Mani

Inventor： Christophe Mani

IPC: H04Q5/22

CPC classification number: G06K7/10029 ,  G06K7/0008

Abstract: An anti-collision method to identify and select contactless electronic modules (MDL) by a terminal is provided. A module may generate a random identification number prior to a communication, and respond to a general or complementary identification request on a time slot that varies according to its identification number. A non-selected module may generate a new random identification number when it receives a complementary identification request. Thus, the time slot of a non-selected module provided in response to a complementary identification request is not statistically the same as its time slot in response to a previous identification request, and it varies according to its identification number (ID).

Abstract translation: 提供了一种通过终端识别和选择非接触电子模块（MDL）的防碰撞方法。 模块可以在通信之前生成随机标识号，并且在根据其标识号变化的时隙上响应一般或补充的标识请求。 未选择的模块可以在接收到补充标识请求时产生新的随机标识号。 因此，响应于补充识别请求而提供的未选择模块的时隙在响应于先前的识别请求时与其时隙在统计上不相同，并且根据其标识号（ID）而变化。

公开(公告)号：US07050111B2

公开(公告)日：2006-05-23

申请号：US10280737

申请日：2002-10-25

Applicant: Diego Coste

Inventor： Diego Coste

IPC: H04N5/10

CPC classification number: H04N5/10 ,  H04N5/126

Abstract: A synchronization process may include detecting successive horizontal synchronization pulses of a video signal, and a phase comparison between the successive detected pulses and the successive transitions of the reference signal for controlling the oscillator of the phase-locked loop. The detection of each horizontal synchronization pulse may include sampling the video signal, low-pass filtering the sampled signal, thresholding the filtered signal for leaving pulses having a level below a threshold. The synchronization process may also include selecting, as a function of predetermined selection criteria, from among the residual pulses within an observation window centered on a transition of the reference signal for the one which corresponds to the horizontal synchronization pulse.

公开(公告)号：US07042039B2

公开(公告)日：2006-05-09

申请号：US10702066

申请日：2003-11-05

Applicant: Pascale Mazoyer ,  Alexandre Villaret ,  Thomas Skotnicki

Inventor： Pascale Mazoyer ,  Alexandre Villaret ,  Thomas Skotnicki

IPC: H01L27/108

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7888

Abstract: An integrated memory circuit includes at least one memory cell formed by a single transistor whose gate (GR) has a lower face insulated from a channel region by an insulation layer containing a succession of potential wells, which are substantially arranged at a distance from the gate and from the channel region in a plane substantially parallel to the lower face of the gate. The potential wells are capable of containing an electric charge which is confined in the plane and can be controlled to move in the plane towards a first confinement region next to the source region or towards a second confinement region next to the drain region so as to define two memory states for the cell.

Abstract translation: 集成存储器电路包括由单个晶体管形成的至少一个存储单元，其栅极（GR）具有通过包含一系列势阱的绝缘层与沟道区域绝缘的下表面，绝缘层基本上布置在与栅极相距一定距离处 并且从基本上平行于栅极的下表面的平面中的沟道区域开始。 势阱能够容纳限制在平面中的电荷，并且可以控制其在平面内朝向源极区域旁边的第一限制区域或靠近漏极区域的第二限制区域移动，以便限定 两个单元的内存状态。

公开(公告)号：US07038285B2

公开(公告)日：2006-05-02

申请号：US10149093

申请日：2000-12-06

Applicant: Hervé Jaouen ,  Thomas Skotnicki ,  Malgorzata Jurczak

Inventor： Hervé Jaouen ,  Thomas Skotnicki ,  Malgorzata Jurczak

IPC: H01L29/82

CPC classification number: G10K9/13 ,  G01D5/242 ,  G01L9/0042 ,  Y10T428/1157 ,  Y10T428/1171 ,  Y10T428/19

Abstract: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.

Abstract translation: 磁传感器包括由导电材料制成的薄的可变形膜，该导电材料形成电容器的第一板，其导通电流。 电容器的第二电容器板包括半导体衬底的掺杂区域。 气体介质层分离两个板。 由于由位于膜的平面中的磁场产生的洛伦兹力的作用并且垂直于通过其传导的电流线，膜变形。 此外，还提供了用于制造该磁传感器的工艺以及使用该磁传感器来测量磁场的装置。