公开(公告)号：US20190190688A1

公开(公告)日：2019-06-20

申请号：US15846560

申请日：2017-12-19

Applicant: STMicroelectronics International N.V.

Inventor： Rupesh Singh ,  Ankur Bal

IPC: H04L7/00

Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

公开(公告)号：US20190158070A1

公开(公告)日：2019-05-23

申请号：US15815989

申请日：2017-11-17

Applicant: STMicroelectronics International N.V.

Inventor： Mohit Singh ,  Ankur Bal

IPC: H03H17/06

Abstract: A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.

公开(公告)号：US10291389B1

公开(公告)日：2019-05-14

申请号：US15923119

申请日：2018-03-16

Applicant: STMicroelectronics International N.V.

Inventor： Gagan Midha

IPC: H03L7/087 ,  H04L7/033 ,  H04L7/00 ,  H03L7/099 ,  H04B1/7073

Abstract: A modulation circuit includes a locked loop circuit with two-point modulation control and a phase-frequency detector configured to compare a reference frequency signal with a feedback frequency signal. A two-point modulation control circuit includes a first modulation path having a controllable gain and coupled to one of the first and second modulation control points and a second modulation path coupled to another of the first and second modulation control points. Gain matching of the first and second modulation paths is accomplished through the operation of a calibration circuit. The calibration circuit includes a phase detector circuit configured to compare the reference frequency signal with the feedback frequency signal to generate a phase detect signal, and a gain control circuit configured to adjust the controllable gain of the first modulation path as a function a correlation of the phase detect signal with signs of the modulation data.

公开(公告)号：US10277207B1

公开(公告)日：2019-04-30

申请号：US15892308

申请日：2018-02-08

Applicant: STMicroelectronics International N.V.

Inventor： Alok Kumar Tripathi ,  Amit Verma ,  Anuj Grover ,  Deepak Kumar Bihani ,  Tanmoy Roy ,  Tanuj Agrawal

IPC: H03K3/00 ,  H03K3/3562 ,  G11C11/412

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

公开(公告)号：US10272684B2

公开(公告)日：2019-04-30

申请号：US15253601

申请日：2016-08-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Simon Dodd ,  David S. Hunt ,  Joseph Edward Scheffelin ,  Dana Gruenbacher ,  Stefan H. Hollinger ,  Uwe Schober ,  Peter Janouch

IPC: B41J2/14 ,  B41J2/175

Abstract: The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support with respect to a direction of ejection of the nozzles, and a semi-flexible support or semi-rigid support that allow the electrical contacts to be moved with respect to a direction of ejection of the nozzles. The semi-flexible and semi-rigid supports allow the die to be up to and beyond a 90 degree angle with respect to a plane of the electrical contacts. The different supports allow for a variety of positions of the microfluidic die with respect to a position of the electrical contacts.

公开(公告)号：US20190113943A1

公开(公告)日：2019-04-18

申请号：US16217872

申请日：2018-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Kapil Kumar TYAGI ,  Nitin GUPTA

IPC: G05F1/575 ,  G05F1/613

Abstract: An electronic device including a low dropout regulator having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node of the electronic device. A method for operating the device to switch into a power on mode includes: turning on the low dropout regulator, removing a DC bias from the second conduction terminal of the transistor, and turning on the transistor. A method for operating the device to switch into a power down mode includes: turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the low dropout regulator.

公开(公告)号：US10264667B2

公开(公告)日：2019-04-16

申请号：US14310601

申请日：2014-06-20

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics S.R.L. ,  STMicroelectronics International N.V.

Inventor： Simon Dodd ,  Joe Scheffelin ,  Dave Hunt ,  Steve Bush ,  Faiz Sherman

IPC: H05K1/02 ,  B41J2/175

Abstract: The present disclosure is directed to a system that is configured to eject fluid vertically away from a thermal microfluidic die for use with scented oils or other fluids. The die is coupled to a rigid planar support board that separates the die from a reservoir of the fluid. The support board includes an opening that is lined with an inert liner that protects an interior surface of the support board from the fluid. The support board includes contact to an external power supply and contacts to the die on a first surface. The die is coupled to this first surface such that the second surface remains free of electrical connections.

公开(公告)号：US10218380B1

公开(公告)日：2019-02-26

申请号：US16036004

申请日：2018-07-16

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: H03M7/00 ,  H03M7/34 ,  H03M7/16 ,  H03K19/20

Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

公开(公告)号：US20190059135A1

公开(公告)日：2019-02-21

申请号：US16106593

申请日：2018-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Akshat Jain ,  Ranajay Mallik

IPC: H05B33/08

CPC classification number: H05B33/0815 ,  H02M1/08 ,  H02M3/156 ,  H02M2001/0006 ,  H02M2001/0025 ,  H02M2001/0032 ,  H05B33/0809 ,  H05B33/0851

Abstract: A circuit includes a voltage converter converting source voltage to supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between first and second node nodes. Feedback circuitry couples the second node to the feedback node when a voltage at the second node exceeds a first overvoltage, in a first mode of operation. The feedback circuitry couples the second node to the feedback node when the voltage at the second node exceeds a second overvoltage less than the first overvoltage, in a second mode of operation. Impedance circuitry is coupled between the first node and a third node and generates an auxiliary supply voltage and an auxiliary ground voltage when the circuit is in both the first and second modes, the auxiliary supply voltage being less than the supply voltage in both the first and second modes.

公开(公告)号：US10198331B2

公开(公告)日：2019-02-05

申请号：US15475277

申请日：2017-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Rakesh Malik

IPC: G06F11/22 ,  G06F11/263 ,  G06F11/273 ,  G06F11/07

Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.