公开(公告)号：US10114761B2

公开(公告)日：2018-10-30

申请号：US15442462

申请日：2017-02-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Wade K. Smith ,  Kostantinos Danny Christidis

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1009 ,  G06F9/38 ,  G06F13/00 ,  G06F13/28

Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available. The fact that finite state machines are reserved to particular quality-of-service levels means that if all such finite state machines for a particular quality-of-service level are used by pending translation requests, then the translation lookaside buffer does not accept more translation requests for that quality-of-service level.

公开(公告)号：US20180307603A1

公开(公告)日：2018-10-25

申请号：US15497162

申请日：2017-04-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Shuai Che

IPC: G06F12/0811 ,  G06F9/50 ,  G06F12/0846

CPC classification number: G06F12/0811 ,  G06F9/5083 ,  G06F12/0848 ,  G06F2212/00

Abstract: Improvements to traditional schemes for storing data for processing tasks and for executing those processing tasks are disclosed. A set of data for which processing tasks are to be executed is processed through a hierarchy to distribute the data through various elements of a computer system. Levels of the hierarchy represent different types of memory or storage elements. Higher levels represent coarser portions of memory or storage elements and lower levels represent finer portions of memory or storage elements. Data proceeds through the hierarchy as “tasks” at different levels. Tasks at non-leaf nodes comprise tasks to subdivide data for storage in the finer granularity memories or storage units associated with a lower hierarchy level. Tasks at leaf nodes comprise processing work, such as a portion of a calculation. Two techniques for organizing the tasks in the hierarchy presented herein include a queue-based technique and a graph-based technique.

公开(公告)号：US10095637B2

公开(公告)日：2018-10-09

申请号：US15267094

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory W. Smaus ,  John M. King ,  Michael D. Achenbach ,  Kevin M. Lepak ,  Matthew A. Rafacz ,  Noah Bamford

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/14 ,  G06F9/52 ,  G06F9/30

Abstract: Techniques for improving execution of a lock instruction are provided herein. A lock instruction and younger instructions are allowed to speculatively retire prior to the store portion of the lock instruction committing its value to memory. These instructions thus do not have to wait for the lock instruction to complete before retiring. In the event that the processor detects a violation of the atomic or fencing properties of the lock instruction prior to committing the value of the lock instruction, the processor rolls back state and executes the lock instruction in a slow mode in which younger instructions are not allowed to retire until the stored value of the lock instruction is committed. Speculative retirement of these instructions results in increased processing speed, as instructions no longer need to wait to retire after execution of a lock instruction.

公开(公告)号：US10078882B2

公开(公告)日：2018-09-18

申请号：US15346395

申请日：2016-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Philip J. Rogers ,  David Gotwalt ,  Tom Frisinger ,  Rex McCrary

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/4818 ,  G06F9/4881 ,  G06F9/5044 ,  G06F2209/5021 ,  G06F2209/509

Abstract: A method of processing commands is provided. The method includes holding commands in queues and executing the commands in an order based on their respective priority. Commands having the same priority are held in the same queue.

公开(公告)号：US10067718B2

公开(公告)日：2018-09-04

申请号：US15274178

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Glennis Eliagh Covington ,  Kevin M. Brandl ,  Nienchi Hu ,  Shannon T. Kesner

IPC: G06F12/00 ,  G06F3/06

Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.

公开(公告)号：US20180246657A1

公开(公告)日：2018-08-30

申请号：US15442511

申请日：2017-02-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski

IPC: G06F3/06 ,  G06F17/30

CPC classification number: G06F16/1744 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/068 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/3077 ,  H03M7/3079 ,  H04L9/3247 ,  H04L63/123 ,  H04L63/126 ,  H04L69/04 ,  H04L2209/30

Abstract: Techniques for handling data compression in which metadata that indicates which portions of data are compressed are which portions of data are not compressed are disclosed. Segments of a buffer referred to as block groups store compressed blocks of data along with uncompressed blocks of data and hash blocks. If a block group includes a block that is a hash of another block in the block group, then the other block is considered to be compressed. If the block group does not include a block that is a hash of another block in the block group, then the blocks in the block group are uncompressed. The hash function to generate the hash is selected to prevent “collisions,” which occur when the data being stored in the buffer is such that it is possible for a hash block and an uncompressed block to be the same.

公开(公告)号：US20180239722A1

公开(公告)日：2018-08-23

申请号：US15958805

申请日：2018-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski ,  Philip J. Rogers

IPC: G06F13/16

CPC classification number: G06F13/1673 ,  G06F13/1684 ,  Y02D10/14

Abstract: A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.

公开(公告)号：US10042576B2

公开(公告)日：2018-08-07

申请号：US15345639

申请日：2016-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Greggory D. Donley

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0895

Abstract: A method and apparatus of compressing addresses for transmission includes receiving a transaction at a first device from a source that includes a memory address request for a memory location on a second device. It is determined if a first part of the memory address is stored in a cache located on the first device. If the first part of the memory address is not stored in the cache, the first part of the memory address is stored in the cache and the entire memory address and information relating to the storage of the first part is transmitted to the second device. If the first part of the memory address is stored in the cache, only a second part of the memory address and an identifier that indicates a way in which the first part of the address is stored in the cache is transmitted to the second device.

公开(公告)号：US10037267B2

公开(公告)日：2018-07-31

申请号：US15299990

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Nuwan S. Jayasena ,  Dong Ping Zhang

IPC: G06F9/45 ,  G06F11/36 ,  G06F8/71 ,  G06F9/30

CPC classification number: G06F11/3688 ,  G06F8/71 ,  G06F9/30101 ,  G06F9/448 ,  G06F9/4843 ,  G06F9/5088

Abstract: Systems, apparatuses, and methods for migrating execution contexts are disclosed. A system includes a plurality of processing units and memory devices. The system is configured to execute any number of software applications. The system is configured to detect, within a first software application, a primitive for migrating at least a portion of the execution context of a source processing unit to a target processing unit, wherein the primitive includes one or more instructions. The execution context includes a plurality of registers. A first processing unit is configured to execute the one or more instructions of the primitive to cause a portion of an execution context of the first processing unit to be migrated to a second processing unit. In one embodiment, executing the primitive instruction(s) causes an instruction pointer value, with an optional offset value, to be sent to the second processing unit.

公开(公告)号：US10031947B2

公开(公告)日：2018-07-24

申请号：US14749063

申请日：2015-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Mayank Daga

IPC: G06F17/30

Abstract: A method and apparatus for performing a top-down Breadth-First Search (BFS) includes performing a first determination whether to convert to a bottom-up BFS. A second determination is performed whether to convert to the bottom-up BFS, based upon the first determination being positive. The bottom-up BFS is performed, based upon the first determination and the second determination being positive. A third determination is made whether to convert from the bottom-up BFS to the top-down BFS, based upon the third determination being positive.