公开(公告)号：US07853286B2

公开(公告)日：2010-12-14

申请号：US11756551

申请日：2007-05-31

Applicant: Ki Seon Ryu ,  Chang Jae Lee ,  Yong Suk Jin

Inventor： Ki Seon Ryu ,  Chang Jae Lee ,  Yong Suk Jin

IPC: H04B7/00

CPC classification number: H04W36/12 ,  H04W48/08 ,  H04W92/18

Abstract: A method uses inter-base station control messages to provide neighbor base station information to mobile subscriber stations in a mobile communication system. The method includes obtaining, at a serving base station, physical channel information of neighbor base stations over a backbone network via, either directly or via a server; periodically transmitting the obtained physical channel information from the serving base station to a mobile subscriber station connected to the serving base station; and measuring, based on the updated physical channel information, signal quality of the at least one neighbor base station at the mobile subscriber station. Thus, the serving base station receives from the neighbor base stations the inter-base station control messages containing the neighbor base station information, updates the information, and provides the updated information to the corresponding mobile subscriber station(s), to be used for a specific purpose such as handover or network entry.

Abstract translation: 一种方法使用基站间控制消息来向移动通信系统中的移动用户台提供相邻基站信息。 该方法包括：通过直接或经由服务器，在服务基站处经由骨干网络获得邻近基站的物理信道信息; 将获得的物理信道信息周期性地从服务基站发送到与服务基站连接的移动用户站; 以及基于更新的物理信道信息来测量移动用户台处的至少一个相邻基站的信号质量。 因此，服务基站从邻近基站接收到包含相邻基站信息的基站间控制消息，更新信息，并将更新的信息提供给相应的移动用户站，以用于 具体目的，如切换或网络输入。

公开(公告)号：US07672696B2

公开(公告)日：2010-03-02

申请号：US12470188

申请日：2009-05-21

Applicant: Chang-Jae Lee ,  Ki-Seon Ryu ,  Beum-Joon Kim

Inventor： Chang-Jae Lee ,  Ki-Seon Ryu ,  Beum-Joon Kim

IPC: H04B1/16 ,  H04W4/00 ,  H04M1/00 ,  H04B1/38 ,  G08C17/00

CPC classification number: H04W52/0235 ,  Y02D70/00

Abstract: A method of performing a ranging process between a base station and a mobile station in sleep mode in a wireless access system, wherein the base station provides the mobile station with an initial notification of a periodic ranging time that occurs during a sleep time interval and during which the mobile station is to perform the ranging process, the initial notification included in a first message, the first message indicating whether the mobile station should terminate sleep mode to receive downlink data, and wherein the base station provides the mobile station with subsequent notifications of periodic ranging times that occur during the sleep time interval, the subsequent notifications indicated in a second message, the second message transmitted to the mobile station as part of the ranging process such that the mobile station performs a plurality of ranging processes within the sleep time interval.

Abstract translation: 一种在无线接入系统中以休眠模式在基站与移动站之间执行测距过程的方法，其中所述基站向所述移动站提供在睡眠时间间隔期间和在休眠期间期间发生的周期性测距时间的初始通知 移动台要执行测距处理的初始通知包括在第一消息中，第一消息指示移动台是否应当终止睡眠模式以接收下行链路数据，并且其中基站向移动台提供随后的通知 在休眠时间间隔期间发生的周期性测距时间，在第二消息中指示的后续通知，将第二消息作为测距过程的一部分发送到移动台，使得移动站在睡眠时间间隔内执行多个测距过程 。

公开(公告)号：US20090291715A1

公开(公告)日：2009-11-26

申请号：US12470139

申请日：2009-05-21

Applicant: Chang-Jae LEE ,  Ki-Seon Ryu ,  Beum-Joon Kim

Inventor： Chang-Jae LEE ,  Ki-Seon Ryu ,  Beum-Joon Kim

IPC: H04B1/40

CPC classification number: H04W52/0235 ,  Y02D70/00

Abstract: A method of performing a ranging process between a base station and a mobile station in sleep mode in a wireless access system, wherein the base station provides the mobile station with an initial notification of a periodic ranging time that occurs during a sleep time interval and during which the mobile station is to perform the ranging process, the initial notification included in a first message, the first message indicating whether the mobile station should terminate sleep mode to receive downlink data, and wherein the base station provides the mobile station with subsequent notifications of periodic ranging times that occur during the sleep time interval, the subsequent notifications indicated in a second message, the second message transmitted to the mobile station as part of the ranging process such that the mobile station performs a plurality of ranging processes within the sleep time interval.

公开(公告)号：US20070133451A1

公开(公告)日：2007-06-14

申请号：US11674991

申请日：2007-02-14

Applicant: Chang-Jae Lee ,  Ki-Seon Ryu ,  Beum-Joon Kim

Inventor： Chang-Jae Lee ,  Ki-Seon Ryu ,  Beum-Joon Kim

IPC: H04B7/185

CPC classification number: H04W52/0235 ,  Y02D70/00

Abstract: A method of performing a ranging process between a base station and a mobile station in sleep mode in a wireless access system, wherein the base station provides the mobile station with an initial notification of a periodic ranging time that occurs during a sleep time interval and during which the mobile station is to perform the ranging process, the initial notification included in a first message, the first message indicating whether the mobile station should terminate sleep mode to receive downlink data, and wherein the base station provides the mobile station with subsequent notifications of periodic ranging times that occur during the sleep time interval, the subsequent notifications indicated in a second message, the second message transmitted to the mobile station as part of the ranging process such that the mobile station performs a plurality of ranging processes within the sleep time interval.

Abstract translation: 一种在无线接入系统中以休眠模式在基站与移动站之间执行测距过程的方法，其中所述基站向所述移动站提供在睡眠时间间隔期间和在休眠期间期间发生的周期性测距时间的初始通知 移动台要执行测距处理的初始通知包括在第一消息中，第一消息指示移动台是否应当终止睡眠模式以接收下行链路数据，并且其中基站向移动台提供随后的通知 在休眠时间间隔期间发生的周期性测距时间，在第二消息中指示的后续通知，将第二消息作为测距过程的一部分发送到移动台，使得移动站在睡眠时间间隔内执行多个测距过程 。

公开(公告)号：US06495920B2

公开(公告)日：2002-12-17

申请号：US09883988

申请日：2001-06-20

Applicant: Chang Jae Lee

Inventor： Chang Jae Lee

IPC: H01L2348

CPC classification number: H01L29/41783 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wiring for a semiconductor device which is suitable for high density device packing, and a method for forming the same, are disclosed. The wiring includes: impurity regions formed in a substrate on both sides of an insulated gate electrode; a first conduction layer formed on the impurity regions; and a second conduction layer formed in contact with the first conduction layer on one side of the gate electrode. The method includes the steps of: forming impurity regions in a substrate on both sides of an insulated gate electrode; forming a first conduction layer on the impurity regions; and forming a second conduction layer in contact on one side of the gate electrode with the first conduction layer.

Abstract translation: 公开了适用于高密度器件封装的半导体器件的接线及其形成方法。 布线包括：形成在绝缘栅电极两侧的基板中的杂质区域; 在杂质区上形成的第一导电层; 以及与栅电极的一侧上的第一导电层接触形成的第二导电层。 该方法包括以下步骤：在绝缘栅电极两侧的衬底中形成杂质区; 在杂质区上形成第一导电层; 以及在栅电极的一侧与第一导电层形成接触的第二导电层。

公开(公告)号：US06344391B1

公开(公告)日：2002-02-05

申请号：US09660337

申请日：2000-09-12

Applicant: Chang-Jae Lee ,  Nae-Hak Park

Inventor： Chang-Jae Lee ,  Nae-Hak Park

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L27/10811 ,  H01L27/10888

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Abstract translation: 半导体器件包括半导体衬底，其具有包括晶体管的第一和第二杂质区的有源区，形成在半导体衬底的有源区上且与半导体衬底隔离的栅极;形成在半导体衬底上的第一绝缘层， 分别暴露第一和第二杂质区的第一和第二接触孔，具有存储电极和平板电极的电容器，所述存储电极通过所述第一接触孔电连接到所述第一杂质区，位线接触焊盘连接 通过第二接触孔电连接到第二杂质区，形成在平板电极上并具有暴露位线接触焊盘的第三接触孔的第二绝缘中间层和形成在第二绝缘中间层上并与位接触的位线 线接触垫通过第三接触孔。

公开(公告)号：US06174774B1

公开(公告)日：2001-01-16

申请号：US09026690

申请日：1998-02-20

Applicant: Chang-Jae Lee

Inventor： Chang-Jae Lee

IPC: H01L21336

CPC classification number: H01L27/10894 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/10873 ,  H01L27/10888

Abstract: A method of fabricating a semiconductor device having a memory device region and a logic device region on a substrate includes the steps of forming first and second gate lines on the substrate at the memory device region and the logic device region, respectively, forming a sidewall insulating layer on both sides of each of the first and second gate lines, forming a plurality of impurity regions in the substrate, forming a silicon nitride layer on the memory device including the first gate lines, forming a silicide layer on the second gate line and impurity regions at the logic device region, and forming an oxide layer on an exposed surface excluding portions over each one of the impurity regions at the memory region and the logic device region, respectively.

Abstract translation: 制造具有衬底上的存储器件区域和逻辑器件区域的半导体器件的方法包括以下步骤：在存储器件区域和逻辑器件区域上分别在衬底上形成第一和第二栅极线，形成侧壁绝缘 在所述第一和第二栅极线中的每一个的两侧上形成层，在所述衬底中形成多个杂质区，在包括所述第一栅极线的存储器件上形成氮化硅层，在所述第二栅极线上形成硅化物层和杂质 区域，并且在暴露表面上分别在存储区域和逻辑器件区域上的每个杂质区域上除去部分之外的氧化物层。

公开(公告)号：US06171930B2

公开(公告)日：2001-01-09

申请号：US09233463

申请日：1999-01-20

Applicant: Chang-Jae Lee ,  Jae-Il Ju

Inventor： Chang-Jae Lee ,  Jae-Il Ju

IPC: H01L2176

CPC classification number: H01L21/3081 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283

Abstract: The present invention relates to a device isolation structure and a device solation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern. The present invention has several advantages concerning manufacturing costs and reliability, some of which being achieved by forming a thermal oxide film in an empty space of the conductive film by which oxygen is permeated thereinto and thus restraining breakdown from being generated between high voltage devices at a high voltage.

Abstract translation: 本发明涉及半导体功率IC中的器件隔离结构和器件固定方法。 根据本发明的器件隔离结构包括：包括高电压区域和低电压区域的半导体衬底; 与半导体衬底的高压器件区域重叠的沟槽和形成在高电压器件区域和低电压器件区域之间的界面区域; 第四绝缘膜，第五绝缘膜和顺序层叠在沟槽中的导电膜; 形成在包括沟槽的半导体衬底上的第一绝缘膜图案; 以及分别形成在所述沟槽上和所述半导体衬底的从所述第一绝缘膜图案露出的所述上表面的一部分上的场绝缘膜。 本发明具有制造成本和可靠性方面的几个优点，其中一些优点是通过在导电膜的空的空间中形成热氧化膜来实现的，氧空气通过氧化膜渗入其中，从而抑制在高压装置之间产生的击穿 高压。

公开(公告)号：US6156601A

公开(公告)日：2000-12-05

申请号：US333961

申请日：1999-06-16

Applicant: Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

Inventor： Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

IPC: G11C11/34 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10844 ,  H01L27/10805

Abstract: A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.

Abstract translation: 动态随机存取存储器（DRAM）被组织为具有电容器对的基本组织单元的矩阵。 每个电容器对具有第一电容器和其中的第二电容器之一。 每个基本组织单元布置如下：在基板上形成作为平行线的第一字线和第二字线; 第一字线位于第一掺杂区和第二掺杂区之间，以限定第一晶体管; 第二字线位于第一晶体管的第二掺杂区域和第三掺杂区域之间，以限定第二晶体管; 位线以与第一字线和第二字线成倾斜的角度位于衬底的第二掺杂区域上; 第一电容器覆盖第一掺杂区域和第一字线，基本上位于第一掺杂区域的中心，经由第一接触孔连接到第一掺杂区域，并且具有六边形平面部分; 覆盖第三掺杂区域和第二字线的第二电容器基本上位于第三掺杂区域的中心，经由第二接触孔连接到第三掺杂区域，并且具有六边形平面部分; 并且基本组织单元的第一掺杂区域，第二掺杂区域和第三掺杂区域中的每一个的中心点可通过假想直线特征线连接。

公开(公告)号：US6078093A

公开(公告)日：2000-06-20

申请号：US961070

申请日：1997-10-30

Applicant: Chang Jae Lee

Inventor： Chang Jae Lee

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/00

CPC classification number: H01L27/10852 ,  H01L28/40

Abstract: A semiconductor device capacitor structure comprises a semiconductor substrate having an impurity diffusion region; an insulating layer formed on the semiconductor substrate and having a contact hole on the impurity diffusion region; a first lower electrode of a half ring type formed on the insulating film along an upper edge of the contact hole; a second lower electrode formed on a surface of the substrate exposed through the contact hole, a wall of the contact hole, and the first lower electrode; a dielectric layer formed on the first and second lower electrodes; and an upper electrode formed on the dielectric layer. This structure increases capacitance, thereby improving the characteristics and reliability of the device.

Abstract translation: 半导体器件电容器结构包括具有杂质扩散区域的半导体衬底; 绝缘层，其形成在所述半导体衬底上并且在所述杂质扩散区上具有接触孔; 沿所述接触孔的上边缘形成在所述绝缘膜上的半环型的第一下电极; 形成在通过接触孔露出的基板的表面上的第二下电极，接触孔的壁和第一下电极; 形成在第一和第二下部电极上的电介质层; 以及形成在电介质层上的上电极。 该结构增加了电容，从而提高了器件的特性和可靠性。