公开(公告)号：US08254179B2

公开(公告)日：2012-08-28

申请号：US13008181

申请日：2011-01-18

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell(s). This voltage level of the blocking voltage is set so that Vdcp

Abstract translation: 非易失性存储器件包括其中的闪存单元阵列和电压发生器。 电压发生器被配置为在闪速存储器编程操作期间产生编程电压（Vpgm），通过电压（Vpass），阻断电压（Vblock）和去耦电压（Vdcp）。 阻塞电压产生在抑制非选择存储单元的无意编程的水平。 该阻塞电压的电压电平被设定为使得Vdcp

公开(公告)号：US20120093425A1

公开(公告)日：2012-04-19

申请号：US13232650

申请日：2011-09-14

Applicant: Chang-Hyun LEE ,  Pil-Kyu PARK ,  Dae-Hee KIM ,  Dae-Sung CHO ,  Min-Woo PARK

Inventor： Chang-Hyun LEE ,  Pil-Kyu PARK ,  Dae-Hee KIM ,  Dae-Sung CHO ,  Min-Woo PARK

IPC: G06K9/36

CPC classification number: H04N19/91 ,  H04N19/30

Abstract: Entropy decoding, after encoding, includes performing symbol decoding on a bitstream of a received residual picture in units of two, three, or four symbols according to a context model which is set in the two, three, or four symbol units, and ordering the decoded coefficients of the residual picture in their original order in the frequency domain. Symbol and level decoding may be performed together. A unique symbol value may be used.

Abstract translation: 熵解码在编码之后，包括根据在两个，三个或四个符号单元中设置的上下文模型以二，三或四个符号为单位对接收到的残留图像的比特流执行符号解码，并排序 在频域中以其原始顺序的残差图像的解码系数。 可以一起执行符号和电平解码。 可以使用唯一的符号值。

公开(公告)号：US20120037975A1

公开(公告)日：2012-02-16

申请号：US13195347

申请日：2011-08-01

Applicant: Byung-Kyu CHO ,  Chang-Hyun Lee ,  Young-Woo Park

Inventor： Byung-Kyu CHO ,  Chang-Hyun Lee ,  Young-Woo Park

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  H01L21/764 ,  H01L27/11521 ,  H01L29/42336

Abstract: A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein.

Abstract translation: 半导体器件具有隔离层图案，多个栅极结构和第一绝缘层图案。 隔离层图案形成在基板上并且在其上具有凹部。 栅极结构在衬底和隔离层图案上彼此间隔开。 第一绝缘层图案形成在基板上并且覆盖该凹槽的栅极结构和内壁。 第一绝缘层图案中具有第一气隙。

公开(公告)号：US20120008423A1

公开(公告)日：2012-01-12

申请号：US12980788

申请日：2010-12-29

Applicant: Dae-Suk KIM ,  Chang-Hyun Lee

Inventor： Dae-Suk KIM ,  Chang-Hyun Lee

IPC: G11C7/10

CPC classification number: G11C7/1078 ,  G11C7/109 ,  G11C29/46

Abstract: A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit.

Abstract translation: 设置电路包括：响应于测试信号选择预定码和外部码之一的选择单元;以及设置信息生成单元，用于响应于由选择单元选择的代码生成设置信息。

公开(公告)号：US20110266608A1

公开(公告)日：2011-11-03

申请号：US13181134

申请日：2011-07-12

Applicant: Chang-Hyun Lee ,  Dong-Gun Park

Inventor： Chang-Hyun Lee ,  Dong-Gun Park

IPC: H01L29/788

CPC classification number: H01L21/265 ,  B82Y10/00 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/792

Abstract: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.

Abstract translation: 在集成电路基板上提供集成电路基板和电荷存储图案的非易失性存储器件。 电荷存储图案具有侧壁，并且在电荷存储图案和集成电路基板之间设置隧道绝缘层。 在电荷存储图案上提供栅极图案。 在电荷存储图案和栅极图案之间设置隔离绝缘层。 电荷存储图案的侧壁包括第一氮掺杂层。 本文还提供了制造非易失性存储器件的相关方法。

公开(公告)号：US08035151B2

公开(公告)日：2011-10-11

申请号：US12382385

申请日：2009-03-16

Applicant: Chang-Hyun Lee ,  Jung-Dal Choi

Inventor： Chang-Hyun Lee ,  Jung-Dal Choi

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/1083

Abstract: A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括至少一个存储器沟道区和至少一个存储源/漏区，存储器沟道区和存储源/漏区被交替排列，以及存储器沟道区上的至少一个字线 其中，所述存储器源极/漏极区域具有比所述存储器沟道区域更高的净杂质浓度。

公开(公告)号：US08008153B2

公开(公告)日：2011-08-30

申请号：US12488061

申请日：2009-06-19

Applicant: Chang-Hyun Lee ,  Dong-Gun Park

Inventor： Chang-Hyun Lee ,  Dong-Gun Park

IPC: H01L21/336

CPC classification number: H01L21/265 ,  B82Y10/00 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/792

Abstract: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.

Abstract translation: 在集成电路基板上提供集成电路基板和电荷存储图案的非易失性存储器件。 电荷存储图案具有侧壁，并且在电荷存储图案和集成电路基板之间设置隧道绝缘层。 在电荷存储图案上提供栅极图案。 在电荷存储图案和栅极图案之间设置隔离绝缘层。 电荷存储图案的侧壁包括第一氮掺杂层。 本文还提供了制造非易失性存储器件的相关方法。

公开(公告)号：US07968931B2

公开(公告)日：2011-06-28

申请号：US12503354

申请日：2009-07-15

Applicant: Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

Abstract translation: 非易失性存储器件包括在半导体衬底上的隧道绝缘层，电荷存储层，阻挡绝缘层和栅电极。 电荷存储层位于隧道绝缘层上，并且具有比隧道绝缘层更小的带隙，并且具有比半导体衬底更大的带隙。 阻挡绝缘层位于电荷存储层上，并且具有比电荷存储层更大的带隙，并且具有比隧道绝缘层更小的带隙。 栅电极位于阻挡绝缘层上。

公开(公告)号：US07808036B2

公开(公告)日：2010-10-05

申请号：US11976389

申请日：2007-10-24

Applicant: Chang-Hyun Lee ,  Jung-dal Choi

Inventor： Chang-Hyun Lee ,  Jung-dal Choi

IPC: G11C16/04

CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

公开(公告)号：US07796440B2

公开(公告)日：2010-09-14

申请号：US12222264

申请日：2008-08-06

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/3454

Abstract: Provided are a NAND flash memory device and a method of programming the same. The NAND flash memory device may include a cell array including a plurality of pages; a page buffer storing program data of the pages; a data storage circuit providing program verification data to the page buffer; and a control unit. The control unit may program the pages and verify the pages using the program verification data following the programming of at least two of the pages.

Abstract translation: 提供了一种NAND闪速存储器件及其编程方法。 NAND闪存器件可以包括包括多个页的单元阵列; 页面缓冲器，其存储页面的程序数据; 数据存储电路，向页缓冲器提供程序验证数据; 和控制单元。 控制单元可以在编程至少两个页面之后使用程序验证数据对页面进行编程并验证页面。