公开(公告)号：US20080181006A1

公开(公告)日：2008-07-31

申请号：US11668087

申请日：2007-01-29

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3486

摘要： A method of programming a memory cell is described. First, a first programming operation is performed to inject electrons into a nitride layer adjacent to a side of a drain. The first programming operation includes applying a first gate voltage to a gate, applying a first drain voltage to the drain, applying a first source voltage to a source, and applying a first substrate, voltage to a substrate. Then, a second programming operation is performed to inject the electrons into the nitride layer adjacent to a side of the source. The second programming operation includes applying a second gate voltage to the gate, applying a second drain voltage to the drain, applying a second source voltage to the source, and applying a second substrate voltage to the substrate. The second gate voltage is less than the first gate voltage.

摘要翻译： 描述了对存储器单元进行编程的方法。 首先，执行第一编程操作以将电子注入到与漏极侧相邻的氮化物层中。 第一编程操作包括向栅极施加第一栅极电压，向漏极施加第一漏极电压，向源施加第一源极电压，以及向衬底施加第一衬底电压。 然后，执行第二编程操作以将电子注入到与源的一侧相邻的氮化物层中。 第二编程操作包括向栅极施加第二栅极电压，向漏极施加第二漏极电压，向源施加第二源电压，以及向衬底施加第二衬底电压。 第二栅极电压小于第一栅极电压。

公开(公告)号：US20080084762A1

公开(公告)日：2008-04-10

申请号：US11601710

申请日：2006-11-20

申请人： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

发明人： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC分类号： G11C11/34

CPC分类号： G11C16/0475

摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

摘要翻译： 公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。 该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

公开(公告)号：US20080023699A1

公开(公告)日：2008-01-31

申请号：US11460209

申请日：2006-07-26

申请人： Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

发明人： Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC分类号： H01L23/58

CPC分类号： H01L22/34 ,  H01L2224/73204 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.

摘要翻译： 半导体工艺测试结构包括电极，电荷俘获层和扩散区域。 测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。 然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

公开(公告)号：US20070297241A1

公开(公告)日：2007-12-27

申请号：US11614905

申请日：2006-12-21

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0475 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568

摘要： Charge trapping memory devices and methods are described for increasing a second bit operation window by a fringe-induced effect. The fringe-induced effect occurs in areas underneath a word line so that when a hole injection method is applied to a memory device, hole charges are stored in a charge trapping layer that intersects with a word line and the hole charges are stored along fringes of the word line. In one embodiment, a virtual ground array comprises a charge trapping layer that is disposed between two dielectrics such that there is not a charge trapping layer over source and drain regions. After a hole injection is applied to the virtual ground array, hole charges are stored along fringes of each word line given the fringes of the word line has a larger electrical field relative to non-fringe areas of the word line.

摘要翻译： 描述了电荷俘获存储器件和方法，用于通过边缘引起的效应来增加第二位操作窗口。 边缘引起的效应发生在字线下方的区域中，使得当空穴注入方法应用于存储器件时，空穴电荷存储在与字线相交的电荷捕获层中，并且孔电荷沿着 字线。 在一个实施例中，虚拟接地阵列包括电荷俘获层，其被设置在两个电介质之间，使得在源极和漏极区域上不存在电荷捕获层。 在向虚拟接地阵列施加空穴注入之后，空穴电荷沿着每个字线的边缘存储，因为字线的边缘相对于字线的非边缘区域具有较大的电场。

公开(公告)号：US20070236994A1

公开(公告)日：2007-10-11

申请号：US11625236

申请日：2007-01-19

申请人： Tzu Hsuan Hsu ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

发明人： Tzu Hsuan Hsu ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C16/02

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

摘要翻译： 本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷俘获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧道法。 本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。 使用衬底瞬态热电子注入进行电荷俘获存储器的编程，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到 电荷捕获结构。

公开(公告)号：US07251167B2

公开(公告)日：2007-07-31

申请号：US11026947

申请日：2004-12-29

申请人： Hsiang-Lan Lung ,  Chao-I Wu

发明人： Hsiang-Lan Lung ,  Chao-I Wu

IPC分类号： G11C16/04

CPC分类号： H01L29/7923

摘要： A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low Vt value. A data region that is to be programmed to a highest Vt value is programmed first. Remaining data regions in the nitride read-only memory cell are programmed in a time order according to their descending Vt values. For a nitride read-only memory cell that, in an erased state, exhibits a high Vt value, a data region that is to be programmed to a lowest Vt value is programmed first with remaining data regions programmed in a time order according to their ascending Vt values.

摘要翻译： 描述了在氮化物只读存储器单元中编程数据区域的方法。 在擦除状态下，氮化物只读存储器单元呈现低V值。 首先编程要编程到最高V SUB值的数据区。 氮化物只读存储器单元中的剩余数据区域按照其下降的V t值的时间顺序被编程。 对于在擦除状态下呈现高V V值的氮化物只读存储器单元，要编程到最低V OUT值的数据区域 首先编程其余数据区域按照时间顺序按照它们的升序值编程。

公开(公告)号：US20070161193A1

公开(公告)日：2007-07-12

申请号：US11327792

申请日：2006-01-06

申请人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

发明人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0475 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

摘要翻译： 包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。 因此，可以实现非常紧凑，高密度的存储器阵列。 存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。 可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

公开(公告)号：US20070138539A1

公开(公告)日：2007-06-21

申请号：US11300813

申请日：2005-12-15

申请人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue

发明人： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC分类号： H01L29/792 ,  H01L21/8238

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

摘要： A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

摘要翻译： 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US07218554B2

公开(公告)日：2007-05-15

申请号：US11160097

申请日：2005-06-08

申请人： Cheng-Hsing Hsu ,  Chao-I Wu ,  Hao-Ming Lien ,  Ming-Hsiang Hsueh

发明人： Cheng-Hsing Hsu ,  Chao-I Wu ,  Hao-Ming Lien ,  Ming-Hsiang Hsueh

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0466

摘要： A method of using a non-volatile memory that utilizes a charge-trapping layer for data storage is described. A refresh step is performed, after the non-volatile memory is subject to multiple write/erase cycles causing hard-to-erase electrons in the charge-trapping layer, to eliminate the hard-to-erase electrons. After the refresh step, the non-volatile memory is used again.

摘要翻译： 描述了使用利用电荷捕获层进行数据存储的非易失性存储器的方法。 在非易失性存储器经受多次写入/擦除周期之后，在电荷俘获层中产生难以擦除的电子的情况下，执行刷新步骤，以消除难以擦除的电子。 刷新步骤后，再次使用非易失性存储器。

公开(公告)号：US07206227B1

公开(公告)日：2007-04-17

申请号：US11326855

申请日：2006-01-06

申请人： Chao-I Wu ,  Ming Hsiu Lee ,  Ming-Chang Kuo

发明人： Chao-I Wu ,  Ming Hsiu Lee ,  Ming-Chang Kuo

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/0466 ,  G11C16/0491

摘要： An Assisted Charge (AC) Memory cell includes a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can include a trapping layer. The trapping layer can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the layer. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency.

摘要翻译： 辅助充电（AC）存储单元包括晶体管，其包括例如p型衬底，其具有植入在p型衬底上的n +源极区和n +漏极区。 栅电极可以形成在衬底上以及源区和漏区的部分之上。 栅电极可以包括捕获层。 捕获层可以被电分为两侧。 一侧可以称为“AC侧”，并且可以通过在层内捕获电子而将其固定在高电压。 电子被称为辅助电荷。 另一边可以用来存储数据，被称为“数据端”。 AC侧和数据侧之间的突发电场可以提高编程效率。