公开(公告)号：US20110114164A1

公开(公告)日：2011-05-19

申请号：US12948279

申请日：2010-11-17

Applicant: Yi-Chieh Lin ,  Shih-Chang Lee

Inventor： Yi-Chieh Lin ,  Shih-Chang Lee

IPC: H01L31/06

CPC classification number: H01L31/0735 ,  Y02E10/544

Abstract: Disclosed is a solar cell including a first base layer, a second base layer on the first base layer, and an emitter layer on the second base layer. Furthermore, a window layer may be disposed on the emitter, and/or a back surface field (BSF) layer may be disposed under the first base layer.

Abstract translation: 公开了一种太阳能电池，其包括第一基底层，第一基底层上的第二基底层和第二基底层上的发射极层。 此外，窗口层可以设置在发射器上，和/或背面场（BSF）层可以设置在第一基底层下方。

公开(公告)号：US20110112666A1

公开(公告)日：2011-05-12

申请号：US12616215

申请日：2009-11-11

Applicant: Brian McFarland ,  Ching-Chieh Lin ,  David Konetski ,  Douglas Peeler

Inventor： Brian McFarland ,  Ching-Chieh Lin ,  David Konetski ,  Douglas Peeler

IPC: G06F17/00

CPC classification number: G06F3/162 ,  H04R5/04

Abstract: An analog connector disposed at an information handling system housing accepts both analog audio information and digital audio information at plural connection surfaces by accepting either an analog or digital jack. An audio subsystem of the information handling system manages audio information at the connector by selectively configuring to handle analog or digital signals based upon the type of jack insert into the connector. Selection of analog or digital management is performed manually through a user interface or automatically by detection of the type of jack inserted in the connector. In one embodiment, a four pole analog connector accepts a four pole digital jack that communicates serial data through a pole connection surface instead of analog signals.

Abstract translation: 设置在信息处理系统壳体上的模拟连接器通过接收模拟或数字插孔来接收多个连接表面的模拟音频信息和数字音频信息。 信息处理系统的音频子系统通过选择性地配置以基于插座插入连接器的类型来处理模拟或数字信号来管理连接器处的音频信息。 通过用户界面手动进行模拟或数字管理的选择，或通过检测插入连接器中的插孔的类型自动进行。 在一个实施例中，四极模拟连接器接受通过极连接表面而不是模拟信号传送串行数据的四极数字插孔。

公开(公告)号：USD637026S1

公开(公告)日：2011-05-03

申请号：US29362082

申请日：2010-05-19

Applicant: Chen-Chieh Lin

Designer： Chen-Chieh Lin

公开(公告)号：US20110084335A1

公开(公告)日：2011-04-14

申请号：US12614434

申请日：2009-11-08

Applicant: Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

Inventor： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

IPC: H01L27/06 ,  H01L21/8234 ,  H01L23/60

CPC classification number: H01L27/0629 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0255 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.

Abstract translation: 具有漏极电压保护的功率半导体器件包括半导体衬底，至少沟槽栅极晶体管器件和至少沟槽ESD保护器件。 半导体衬底的上表面具有第一沟槽和第二沟槽。 沟槽栅极晶体管器件设置在第一沟槽和半导体衬底中。 沟槽ESD保护器件设置在第二沟槽中，并且包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域和第三掺杂区域分别电连接到沟槽栅极晶体管器件的漏极和栅极。

公开(公告)号：US20110007542A1

公开(公告)日：2011-01-13

申请号：US12833131

申请日：2010-07-09

Applicant: Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

Inventor： Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

IPC: G11C17/00 ,  G11C29/00

CPC classification number: G11C17/16 ,  G11C17/14 ,  G11C29/08

Abstract: A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern, that is, having repeats of one user cell and one test cell in both column and row directions. Programming the test section and various additional tests are performed to both the user and test sections and other circuitry of the memory array while the user section is not programmed. Even though the OTP user section is not programmed or tested, the provided tests in accordance with embodiments of the invention can provide a very high probability that the OTP memory including the user section is of high quality, i.e., the OTP cells in the user section can be programmed and function appropriately.

Abstract translation: 一次性编程（OTP）存储器阵列分为用户部分和测试部分。 用户部分和测试部分中的单元格被配置为形成棋盘图案，即在列和行方向上具有一个用户单元和一个测试单元的重复。 在用户部分未编程的情况下，对测试部分进行编程，并对存储器阵列的用户和测试部分以及其他电路进行各种附加测试。 即使OTP用户部分未被编程或测试，根据本发明的实施例提供的测试可以提供包括用户部分的OTP存储器具有高质量（即，用户部分中的OTP单元）的非常高的概率 可以编程并正常工作。

公开(公告)号：US20100332734A1

公开(公告)日：2010-12-30

申请号：US12721724

申请日：2010-03-11

Applicant: Yeow-Chyi Chen ,  Hong-Ching Chen ,  Li-Chun Tu ,  Tzu-Chieh Lin ,  Chi-Wei Peng

Inventor： Yeow-Chyi Chen ,  Hong-Ching Chen ,  Li-Chun Tu ,  Tzu-Chieh Lin ,  Chi-Wei Peng

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F13/1684 ,  Y02D10/14

Abstract: A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.

Abstract translation: 闪存器件包括存储器阵列和存储器控制电路。 存储器阵列包括存储器模块。 每个存储器模块位于存储器通道中并且包括预定数量的存储器单元。 存储器控制电路通过地址锁存使能（ALE）引脚和命令锁存使能（CLE）引脚耦合到存储器阵列。 ALE引脚和CLE引脚耦合到所有存储单元，并由存储器阵列中的所有存储单元共享。

公开(公告)号：US07851310B2

公开(公告)日：2010-12-14

申请号：US12483237

申请日：2009-06-11

Applicant: Li-Cheng Lin ,  Wei-Chieh Lin

Inventor： Li-Cheng Lin ,  Wei-Chieh Lin

IPC: H01L21/338

CPC classification number: H01L29/4236 ,  H01L29/66621 ,  H01L29/78

Abstract: A method for forming semiconductor device, which simultaneously forms a trench MOS transistor device, and an embedded schottky barrier diode (SBD) device in a semiconductor substrate. The embedded SBD device has lower forward voltage drop, which reduces power dissipation. In addition, the voltage bearing ability may be modified easily by virtue of altering the dopant concentration or the width of the voltage bearing dopant region, or the thickness of epitaxial silicon layer. Furthermore, extra cost of purchasing SBD diode may be saved.

Abstract translation: 一种在半导体衬底中同时形成沟槽MOS晶体管器件和嵌入肖特基势垒二极管（SBD）器件的半导体器件的形成方法。 嵌入式SBD器件具有较低的正向压降，从而降低功耗。 此外，由于改变掺杂剂掺杂剂区域的掺杂剂浓度或宽度，或外延硅层的厚度，可以容易地改变电压承载能力。 此外，可以节省购买SBD二极管的额外成本。

公开(公告)号：US20100216290A1

公开(公告)日：2010-08-26

申请号：US12483237

申请日：2009-06-11

Applicant: Li-Cheng Lin ,  Wei-Chieh Lin

Inventor： Li-Cheng Lin ,  Wei-Chieh Lin

IPC: H01L21/336

CPC classification number: H01L29/4236 ,  H01L29/66621 ,  H01L29/78

Abstract: A method for forming semiconductor device, which simultaneously forms a trench MOS transistor device, and an embedded schottky barrier diode (SBD) device in a semiconductor substrate. The embedded SBD device has lower forward voltage drop, which reduces power dissipation. In addition, the voltage bearing ability may be modified easily by virtue of altering the dopant concentration or the width of the voltage bearing dopant region, or the thickness of epitaxial silicon layer. Furthermore, extra cost of purchasing SBD diode may be saved.

公开(公告)号：US07759832B2

公开(公告)日：2010-07-20

申请号：US10942990

申请日：2004-09-17

Applicant: Ko-Chieh Lin ,  Lee-Long Chen ,  Wen-Tsao Lee ,  Kuo-Tung Hsu

Inventor： Ko-Chieh Lin ,  Lee-Long Chen ,  Wen-Tsao Lee ,  Kuo-Tung Hsu

IPC: H02K5/16

CPC classification number: F04D29/051 ,  F04D25/062

Abstract: A fan includes a frame, a stator, a rotor and a magnetic member. The frame comprises a base. The stator is connected to the frame. The rotor has a shaft. The magnetic member, corresponding to the shaft, is disposed on the base to attract the shaft. The magnetic member and the shaft are spaced apart with the base disposed therebetween. The magnetic member may be disposed outside or inside the frame or on the stator.

Abstract translation: 风扇包括框架，定子，转子和磁性构件。 框架包括底座。 定子连接到框架。 转子有一个轴。 对应于轴的磁性构件设置在基座上以吸引轴。 磁性构件和轴与其间设置的基座间隔开。 磁性构件可以设置在框架内部或内部或定子上。

公开(公告)号：US07733096B2

公开(公告)日：2010-06-08

申请号：US11731960

申请日：2007-04-02

Applicant: Sung-Chieh Lin ,  Po-Hung Chen

Inventor： Sung-Chieh Lin ,  Po-Hung Chen

IPC: G01R31/02

CPC classification number: G11C29/02 ,  G11C17/165 ,  G11C29/027

Abstract: A method of testing a fuse element for a memory device is provided. A first test probe is electrically connected to a program terminal of the memory device. A second test probe is electrically connected to a ground terminal. The fuse element is on an electrical circuit path between the program terminal and the ground terminal. The first and second test probes are electrically connected to a testing device. A first voltage is applied with the testing device between the program terminal and the ground terminal. At least part of a first current of the first voltage flows across the fuse element. The first voltage and the at least part of the first current that flows across the fuse element is not large enough to change the conductivity state of the fuse element. The first current is measured and used to evaluated the conductive state of the fuse element.

Abstract translation: 提供一种测试用于存储器件的熔丝元件的方法。 第一测试探针电连接到存储器件的程序终端。 第二测试探针电连接到接地端子。 保险丝元件位于程序端子和接地端子之间的电路上。 第一和第二测试探针电连接到测试装置。 测试设备在程序终端和接地端子之间施加第一个电压。 第一电压的第一电流的至少一部分流过熔丝元件。 在熔断元件上流动的第一电流和第一电流的至少一部分不足以改变熔丝元件的导电状态。 测量第一电流并用于评估熔丝元件的导电状态。