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    Memory controller for daisy chained memory chips
    61.
    发明授权
    Memory controller for daisy chained memory chips 失效
    内存控制器，用于菊花链式存储芯片

    公开(公告)号：US07627711B2

    公开(公告)日：2009-12-01

    申请号：US11459966

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F12/06

    CPC分类号： G06F13/4243 ,  G06F13/4256

    摘要： A memory controller configured to control a daisy chain of memory chips. The memory controller receives read and write requests from a processor, determines a daisy chain of memory chips that the request is directed to, determines which memory chip in the chain of memory chips the request is directed to, and transmits an address/command word recognizable by the correct memory chip. The memory controller sends write data words to the daisy chain of memory chips that can be associated by the correct memory chip for writing into the correct memory chip. The memory controller receives read data words from the daisy chain of memory chips and returns the read data to the processor. The memory controller transmits a bus clock to the daisy chain of memory chips for controlling transmission of address/command words and data words.

    摘要翻译： 存储器控制器，被配置为控制存储器芯片的菊花链。 存储器控制器从处理器接收读取和写入请求，确定请求所针对的存储器芯片的菊花链，确定请求所针对的存储器芯片链中的哪个存储器芯片，并发送可识别的地址/命令字 由正确的内存芯片。 存储器控制器将写数据字发送到存储器芯片的菊花链，其可由正确的存储器芯片关联以写入正确的存储器芯片。 存储器控制器从存储器芯片的菊花链接收读取的数据字，并将读取的数据返回给处理器。 存储器控制器将总线时钟发送到存储器芯片的菊花链，用于控制地址/命令字和数据字的传输。

    Memory Controller for Daisy Chained Self Timed Memory Chips
    66.
    发明申请
    Memory Controller for Daisy Chained Self Timed Memory Chips 失效
    用于菊花链自定时存储器芯片的存储控制器

    公开(公告)号：US20080028177A1

    公开(公告)日：2008-01-31

    申请号：US11459961

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1668

    摘要： A memory controller for controlling a daisy chain of self timed memory chips. The memory controller has information as to how long each self timed memory chip in the daisy chain of memory chips takes to make a read access and a write access to an array on the self timed memory chip. The memory controller determines current access time information on a memory chip by sending a command to the memory chip. The memory chip returns a data word containing the current access time information. Alternatively, the memory controller transmits an address/command word to the memory chip and, after completing an access, transmits a responsive data word to the memory controller. The memory controller determines the access time information using the interval from transmission of the address/command word to reception of the responsive data word.

    摘要翻译： 用于控制自定时存储器芯片的菊花链的存储器控​​制器。 存储器控制器具有关于存储器芯片的菊花链中的每个自定时存储器芯片对自定时存储器芯片进行读取访问和写入访问多长时间的信息的信息。 存储器控制器通过向存储器芯片发送命令来确定存储器芯片上的当前访问时间信息。 存储器芯片返回包含当前访问时间信息的数据字。 或者，存储器控制器将地址/命令字发送到存储器芯片，并且在完成访问之后，将响应数据字发送到存储器控制器。 存储器控制器使用从地址/命令字的发送到响应数据字的接收的间隔来确定访问时间信息。

    CARRIER HAVING DAISY CHAIN OF SELF TIMED MEMORY CHIPS
    67.
    发明申请
    CARRIER HAVING DAISY CHAIN OF SELF TIMED MEMORY CHIPS 失效
    具有自定义记忆卡的DAISY链的承运人

    公开(公告)号：US20080028160A1

    公开(公告)日：2008-01-31

    申请号：US11459983

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F13/00 ,  G06F12/00

    CPC分类号： G06F13/1684 ,  G11C7/10

    摘要： A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.

    摘要翻译： 一种在存储器芯片的菊花链中具有至少一个自定时存储器芯片的载体。 第一载体具有连接到第一载体的存储芯片的菊链的至少一部分。 第一载波上的地址/命令总线输入将地址/命令字携带到存储器芯片的菊花链中的第一存储器芯片。 如果第一存储器芯片确定地址/命令字不指向第一存储器芯片，则第一存储器芯片使用点对点将地址/命令字重新驱动到存储器芯片的菊花链中的第二存储器芯片 地址/命令总线链路。 如果第一个载波上没有更多的存储器芯片，则地址/命令字被重新驱动到地址/命令总线非承载连接器。 存储器芯片上的阵列具有动态确定阵列可访问速度的访问时间。

    Computer System Having an Apportionable Data Bus
    68.
    发明申请
    Computer System Having an Apportionable Data Bus 有权
    具有可分配数据总线的计算机系统

    公开(公告)号：US20080028125A1

    公开(公告)日：2008-01-31

    申请号：US11459955

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1678 ,  G06F13/1684

    摘要： A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated to transmitting data from the memory to the memory controller. The apportionment can be assigned by suitable connection of pins on a memory chip in the memory and the memory controller to logical values. Alternatively, the apportionment can be scanned into the memory controller and the memory at bring up time. In another alternative, the apportionment can be changed by suspending data transfer and dynamically changing the sizes of the first portion and the second portion.

    摘要翻译： 具有耦合存储器控制器和存储器的数据总线的存储器系统。 数据总线具有多个数据总线位。 数据总线可编程地分配给专用于从存储器控制器向存储器发送数据的第一部分和专用于将数据从存储器传送到存储器控制器的第二部分。 分配可以通过将存储器中的存储器芯片上的引脚适当地连接到存储器控制器到逻辑值来分配。 或者，可以在释放时间的情况下将分配扫描到存储器控制器和存储器中。 在另一替代方案中，可以通过暂停数据传送和动态地改变第一部分和第二部分的大小来改变分配。

    COMPUTER SYSTEM HAVING DAISY CHAINED SELF TIMED MEMORY CHIPS
    69.
    发明申请
    COMPUTER SYSTEM HAVING DAISY CHAINED SELF TIMED MEMORY CHIPS 有权
    具有自动链接的自定义记忆卡的计算机系统

    公开(公告)号：US20080025130A1

    公开(公告)日：2008-01-31

    申请号：US11459968

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G11C8/00 ,  G11C5/06

    CPC分类号： G11C5/00 ,  G11C7/10

    摘要： A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on each memory chip is determined by a self time block on each memory chip.

    摘要翻译： 一种具有存储器系统的计算机系统，所述存储器系统具有存储器控制器和存储器。 存储器包括一个或多个自定时存储器芯片的菊花链。 地址/命令字通过存储器芯片的菊花链链接并由存储器芯片的菊花链中的一个存储器芯片来处理。 作为地址/命令字的一部分发送要写入存储器芯片的数据，或者在输出数据总线链上传送。 从存储芯片读取的数据在传入数据总线链上传输。 每个存储器芯片上的访问定时由每个存储器芯片上的自身时间块确定。

    Socket assembly with incorporated memory structure
    70.
    发明授权
    Socket assembly with incorporated memory structure 失效
    内置内存结构的插座组合

    公开(公告)号：US07074050B1

    公开(公告)日：2006-07-11

    申请号：US11282083

    申请日：2005-11-17

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： H01R12/00

    CPC分类号： H01R13/22 ,  H01R12/7076

    摘要： A socket assembly with incorporated memory structure is provided. A chip carrier socket assembly includes dual stage clamping actuation. A first clamping actuation stage provides clamping force for ball grid array (BGA) contact pads and a second clamping actuation stage provides clamping force for a thermal interface. The first clamping actuation stage provides clamping force proximate to a perimeter of a carrier where a plurality of BGA contact pads are located. The second clamping actuation stage provides clamping force generally centrally of the chip carrier socket assembly for thermal interface actuation.

    摘要翻译： 提供具有内置存储器结构的插座组件。 芯片载体插座组件包括双级夹紧致动。 第一夹紧致动台为球栅阵列（BGA）接触垫提供夹紧力，第二夹紧致动台为热界面提供夹紧力。 第一夹紧致动台提供靠近其中定位有多个BGA接触垫的载体的周边的夹紧力。 第二夹紧致动台提供通常位于芯片承载器插座组件中心的用于热接口致动的夹紧力。