Voltage measuring apparatus and battery management system including the same

    公开(公告)号:US09645201B2

    公开(公告)日:2017-05-09

    申请号:US14189212

    申请日:2014-02-25

    发明人: Moonsik Song Seok Heo

    IPC分类号: H02J7/00 H02J7/14 G01R31/36

    摘要: The voltage measuring apparatus is connected to a plurality of battery cells connected to each other in series to measure respective voltages of the battery cells. The voltage measuring apparatus includes a sample/hold amplifier configured to sample and hold positive electrode and negative electrode voltages of the battery cells to generate first and second output voltages, a differential voltage converter configured to generate a battery cell voltage according to a voltage difference between a positive input terminal and a negative input terminal, and a switching unit configured to control the first and second output voltages and connection between the positive input terminal and the negative input terminal so that a polarity of the voltage difference is constant. The sample/hold amplifier electrically insulates the switching unit from the battery cells.

    SUPERJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    69.
    发明申请
    SUPERJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    超级半导体器件及其制造方法

    公开(公告)号:US20170054009A1

    公开(公告)日:2017-02-23

    申请号:US15242018

    申请日:2016-08-19

    摘要: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.

    摘要翻译: 超结半导体器件包括掺杂有第一导电类型的第一半导体层; 形成在所述第一半导体层上的有源区,所述有源区包括漂移层; 以及设置成围绕所述有源区域的端接区域,所述端接区域包括设置在所述漂移层的侧表面上的下边缘区域和设置在所述下边缘区域上的上边缘区域,其中所述上边缘区域包括较低的电荷平衡 所述下电荷平衡区具有不同于所述第一导电类型的第二导电类型,以及设置在所述下电荷平衡区上的上电荷平衡区,所述上电荷平衡区具有第一导电类型。

    POWER-ON RESET CIRCUIT AND UNDER-VOLTAGE LOCKOUT CIRCUIT COMPRISING THE SAME
    70.
    发明申请
    POWER-ON RESET CIRCUIT AND UNDER-VOLTAGE LOCKOUT CIRCUIT COMPRISING THE SAME 审中-公开
    上电复位电路和包含相同的欠压锁定电路

    公开(公告)号:US20170012619A1

    公开(公告)日:2017-01-12

    申请号:US15204138

    申请日:2016-07-07

    IPC分类号: H03K17/22

    摘要: An UVLO circuit according to an aspect of the present invention includes: a power-on reset (POR) circuit generating an output based on a first current that flows according to an increase of a power supply voltage and not operating in a normal state of the power supply voltage; and a logic operation unit generating a reset signal according to an output of the POR circuit and an output based on a result of comparison between a sense voltage that corresponds to the power supply voltage and a predetermined reference voltage.

    摘要翻译: 根据本发明的一个方面的UVLO电路包括:上电复位(POR)电路,其基于根据电源电压的增加而流动的第一电流产生输出,而不是在正常状态下工作 电源电压; 以及逻辑运算单元,根据POR电路的输出和基于对应于电源电压的感测电压与预定参考电压之间的比较结果产生复位信号。