公开(公告)号：US08278687B2

公开(公告)日：2012-10-02

申请号：US12058101

申请日：2008-03-28

Applicant: Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Robert S. Chau

IPC: H01L29/778

CPC classification number: H01L29/7783 ,  H01L29/42316 ,  H01L29/7784

Abstract: Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap.

Abstract translation: 通常描述用于减少短通道效应的半导体异质结构。 在一个示例中，设备包括半导体衬底，耦合到半导体衬底的一个或多个缓冲层，耦合到一个或多个缓冲层的第一势垒层，耦合到第一阻挡层的背栅层，其中背栅层 包括III-V族半导体材料，II-VI族半导体材料或其组合，所述背栅层具有第一带隙，耦合到所述背栅层的第二阻挡层，其中所述第二阻挡层包括III- V族半导体材料，II-VI族半导体材料或其组合，所述第二阻挡层具有相对大于所述第一带隙的第二带隙，以及耦合到所述第二阻挡层的量子阱沟道，所述量子阱沟道具有 相对小于第二带隙的第三带隙。

公开(公告)号：US20120231596A1

公开(公告)日：2012-09-13

申请号：US13479121

申请日：2012-05-23

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L21/335

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US08258543B2

公开(公告)日：2012-09-04

申请号：US12632498

申请日：2009-12-07

Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract translation: 描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。

公开(公告)号：US20110211402A1

公开(公告)日：2011-09-01

申请号：US13069333

申请日：2011-03-22

Applicant: Titash Rakshit ,  Gilbert Dewey ,  Ravi Pillarisetty

Inventor： Titash Rakshit ,  Gilbert Dewey ,  Ravi Pillarisetty

IPC: G11C7/00

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/205 ,  H01L29/7841

Abstract: Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell.

Abstract translation: 本发明的实施例涉及使用具有改进的功耗特性的存储单元的装置，系统和方法，其与浮体单元一起使用低带隙材料量子阱结构。

公开(公告)号：US07999351B2

公开(公告)日：2011-08-16

申请号：US12215322

申请日：2008-06-25

Applicant: Matthew Metz ,  Gilbert Dewey

Inventor： Matthew Metz ,  Gilbert Dewey

IPC: H01L29/92

CPC classification number: H01L21/31645 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3162 ,  H01L21/31641 ,  H01L28/40 ,  H01L28/90

Abstract: Embodiments of a phase-stable amorphous high-κ dielectric layer in a device and methods for forming the phase-stable amorphous high-κ dielectric layer in a device are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 相稳定的非晶高分子化合物的实施方案 器件中的介电层和用于形成相稳定非晶高分子化合物的方法; 这里通常描述器件中的介电层。 可以描述和要求保护其他实施例。

公开(公告)号：US07964866B2

公开(公告)日：2011-06-21

申请号：US12119234

申请日：2008-05-12

Applicant: Titash Rakshit ,  Gilbert Dewey ,  Ravi Pillarisetty

Inventor： Titash Rakshit ,  Gilbert Dewey ,  Ravi Pillarisetty

IPC: H01L49/00 ,  H01L29/12 ,  H01L29/778

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/205 ,  H01L29/7841

Abstract: Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell.

Abstract translation: 本发明的实施例涉及使用具有改进的功耗特性的存储单元的装置，系统和方法，其与浮体单元一起使用低带隙材料量子阱结构。

公开(公告)号：US20110133168A1

公开(公告)日：2011-06-09

申请号：US12632498

申请日：2009-12-07

Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Robert S. Chau ,  Matthew V. Metz

IPC: H01L29/12 ,  H01L21/336

CPC classification number: H01L29/66666 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract translation: 描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。

公开(公告)号：US20110121385A1

公开(公告)日：2011-05-26

申请号：US13017309

申请日：2011-01-31

Applicant: Brian S. Doyle ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Brian S. Doyle ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L27/092

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

Abstract translation: 通常描述嵌入式沟道阵列晶体管（RCAT）结构和形成方法。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的第一鳍，第一鳍包括第一源极区和第一漏极区，以及形成凹陷沟道阵列晶体管（RCAT）的第一栅极结构 在设置在第一源极区域和第一漏极区域之间的第一栅极区域中，其中通过去除牺牲栅极结构以暴露第一栅极区域中的第一鳍片而形成第一栅极结构，将沟道结构凹入第一鳍片， 以及在所述凹陷通道结构上形成所述第一栅极结构。

公开(公告)号：US07888221B2

公开(公告)日：2011-02-15

申请号：US12229459

申请日：2008-08-22

Applicant: Jack T. Kavalieros ,  Matthew V. Metz ,  Gilbert Dewey ,  Been-Yih Jin ,  Justin K. Brask ,  Suman Datta ,  Robert S. Chau

Inventor： Jack T. Kavalieros ,  Matthew V. Metz ,  Gilbert Dewey ,  Been-Yih Jin ,  Justin K. Brask ,  Suman Datta ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L29/7391

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Abstract translation: 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区。

公开(公告)号：US20100327377A1

公开(公告)日：2010-12-30

申请号：US12459254

申请日：2009-06-26

Applicant: Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

Inventor： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/31 ,  H01L21/3205

CPC classification number: H01L29/517 ,  H01B1/122 ,  H01L21/048 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7853 ,  H01L31/022466 ,  H01L31/022475 ,  H01L33/0041 ,  H01L33/40 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L51/102 ,  H01L51/105 ,  H01L51/441 ,  H01L51/442 ,  H01L51/5203 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/306 ,  H01L2251/308 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

Abstract translation: 使用中间层来减少具有半导体衬底的半导体器件中的费米能级钉扎现象。 中间层可以是稀土氧化物。 中间层可以是离子半导体。 金属阻挡膜可以设置在中间层和金属耦合器之间。 中间层可以是金属阻挡膜和半导体基板的热处理组合。 形成中间层的方法可以包括对中间层进行分级。 计算系统包括中间层。