公开(公告)号：US20020101269A1

公开(公告)日：2002-08-01

申请号：US09996448

申请日：2001-11-28

Applicant: INTERSIL AMERICAS INC.

Inventor： James W. Swonger

IPC: H03K003/037

CPC classification number: H03F1/526

Abstract: A spatial and complementary polarity device redundancy-based analog circuit architecture mitigates against single event transients. At least one and preferably multiple redundant spatially separate copies of the complementary device-configured analog circuit (such as a voltage reference or an operational amplifier) are coupled in parallel to the circuit's output node, via a complementary polarity device path. The parallel inputs to the multiple spaced apart devices make the likelihood of a single particle passing through multiple circuits at the same time extremely remote, so that the intended value of the electrical parameter will be sustained by either the given circuit itself or any circuit copy at which the upset event does not occur.

Abstract translation: 基于空间和互补极性设备冗余的模拟电路架构可以缓解单一事件瞬变。 补充器件配置的模拟电路（例如电压基准或运算放大器）的至少一个并且优选地多个冗余的空间上分开的副本经由互补极性器件路径并联连接到电路的输出节点。 多个间隔开的器件的并行输入使得单个粒子同时穿过多个电路的可能性极其遥远，使得电参数的预期值将由给定电路本身或任何电路副本 不会发生不适的事件。

公开(公告)号：US20020024386A1

公开(公告)日：2002-02-28

申请号：US09928857

申请日：2001-08-13

Applicant: Intersil Americas Inc.

Inventor： William Shearon ,  Salomon Vulih ,  Donald Preslar

IPC: H03F003/04

CPC classification number: H03K17/063 ,  H03F2200/504 ,  H03K17/0822

Abstract: The integrated circuit includes a power FET for generating an output voltage, a pilot FET for sensing current through the power driving device and generating a reference voltage, and an amplifier circuit for comparing the reference voltage of the pilot device with the output voltage of the power driving device. The amplifier circuit includes a differential pair of matched bipolar junction transistors (BJTs) having a common base. A first BJT of the differential pair being diode-connected. The amplifier circuit controls the gates of the power FET and the pilot FET.

Abstract translation: 集成电路包括用于产生输出电压的功率FET，用于感测通过功率驱动装置的电流并产生参考电压的引导FET，以及用于将导频装置的参考电压与功率的输出电压进行比较的放大器电路 驱动装置 放大器电路包括具有公共基极的差分对匹配双极结型晶体管（BJT）。 差分对的第一个BJT是二极管连接的。 放大器电路控制功率FET和引导FET的栅极。

公开(公告)号：US20020021175A1

公开(公告)日：2002-02-21

申请号：US09901260

申请日：2001-07-09

Applicant: Intersil Americas Inc.

Inventor： Leonel Ernesto Enriquez

IPC: H03F003/45

CPC classification number: H03F3/3066

Abstract: A transconductance amplifier-based, rectifier circuit architecture is configured to programmably provide normal or inverted, half-wave or full-wave rectification of a single ended or differentially derived input signal. The output current produced by commonly connected outputs of current mirror circuits of the transconductance amplifier's output stage from its power supply terminals is coupled through a first pair of opposite polarity rectifier elements to a first pair of rectifier terminals. The current mirrors include additional current mirror outputs coupled to auxiliary current mirror stages, whose outputs are coupled through a second pair of opposite polarity rectifier elements to a second pair of rectifier terminals. Respective ones of the first and second pairs of rectifier terminals are programmably coupled to ground or to a single ended input terminal of an output amplifier stage. Depending on this set of programmable connections, the output amplifier stage provides one of a normal or inverted, half-wave or a full-wave rectified voltage output signal.

Abstract translation: 基于跨导放大器的整流器电路架构被配置为可编程地提供单端或差分导出的输入信号的正常或反相，半波或全波整流。 跨导放大器的输出级的电流镜电路的共同连接的输出从其电源端子产生的输出电流通过第一对相反极性的整流器元件耦合到第一对整流器端子。 电流镜包括耦合到辅助电流镜级的附加电流镜输出，其输出通过第二对相反极性整流器元件耦合到第二对整流器端子。 第一对和第二对整流器端子中的各个可编程地耦合到输出放大器级的地或单端输入端。 根据这组可编程连接，输出放大器级提供正常或反相，半波或全波整流电压输出信号之一。

公开(公告)号：US09276779B2

公开(公告)日：2016-03-01

申请号：US14513905

申请日：2014-10-14

Applicant: INTERSIL AMERICAS INC.

Inventor： Christopher Keith Davis ,  Jeffrey David Lies

IPC: H04B1/38 ,  H04L25/02

CPC classification number: H04L25/0276 ,  H04L25/0292

Abstract: Systems and methods for providing a full fail-safe capability in signal transmission networks are disclosed. For example, a system for providing a full fail-safe capability in signal transmission networks includes at least a first electronic circuit to transmit and receive signals or data, at least one driver unit coupled to the at least a first electronic circuit, and at least one receiver unit coupled to the at least a first electronic circuit and the at least one driver unit. The at least one receiver unit includes at least one offset signal generating unit, a signal comparing unit, and a switching unit to couple an offset signal from the at least one offset signal generating unit to an input of the signal comparing unit.

公开(公告)号：USRE45814E1

公开(公告)日：2015-11-24

申请号：US13950481

申请日：2013-07-25

Applicant: INTERSIL AMERICAS INC.

Inventor： James D. Beasom

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/7816 ,  H01L29/7835

Abstract: In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the source by a gate, and an extension region doped to a second conductivity type underlying at least a portion of the drain extension adjacent to the gate. The integrated circuit structure also comprises a second complementary MOS device comprising a dual drain extension structure.

公开(公告)号：USRE45773E1

公开(公告)日：2015-10-20

申请号：US14170025

申请日：2014-01-31

Applicant: INTERSIL AMERICAS INC.

Inventor： Michael J. Houston ,  Christopher S. Saunders

IPC: G05F1/40 ,  H02M3/158

CPC classification number: H02M3/1584 ,  H02M3/1588 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

Abstract: A method for operating a voltage regulator controller, for use in a voltage regulator including coupled inductors, is provided as follows. A first signal is generated for driving a first switch of the voltage regulator. A second signal is generated driving a first switch of the voltage regulator. The voltage regulator determines whether a light-load condition exists. Upon determining the existence of a light-load condition, adjusting the phase difference between said first and second signals so that the first and second signals are approximately in-phase.

Abstract translation: 一种用于操作电压调节器控制器的方法，用于包括耦合电感器的电压调节器中，如下。 产生用于驱动电压调节器的第一开关的第一信号。 产生驱动电压调节器的第一开关的第二信号。 电压调节器确定是否存在轻载条件。 在确定轻载条件的存在时，调整所述第一和第二信号之间的相位差，使得第一和第二信号大致同相。

公开(公告)号：US08652960B2

公开(公告)日：2014-02-18

申请号：US13717942

申请日：2012-12-18

Applicant: Intersil Americas Inc.

Inventor： John T. Gasner ,  Michael D. Church ,  Sameer D. Parab ,  Paul E. Bakeman, Jr. ,  David A. Decrosta ,  Robert Lomenick ,  Chris A. McCarty

IPC: H01L21/44

CPC classification number: H01L21/76801 ,  H01L21/32051 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/528 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2224/45099

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract translation: 半导体结构包括顶部金属层，形成在顶部金属层上的接合焊盘，形成在顶部金属层下面的导体以及将导体与顶部金属层分开的绝缘层。 与顶部金属层的剩余部分相比，顶部金属层包括相对刚性材料的子层。 相对硬的材料的子层被配置为在绝缘层上分布应力以减少绝缘层中的开裂。

公开(公告)号：US20130223550A1

公开(公告)日：2013-08-29

申请号：US13706290

申请日：2012-12-05

Applicant: INTERSIL AMERICAS INC.

Inventor： Mark FIMOFF ,  Greg TOMEZAK

IPC: H04L27/34

CPC classification number: H04L27/36 ,  H04L1/0045 ,  H04L1/0054 ,  H04L1/0057 ,  H04L1/0071 ,  H04L5/0007 ,  H04L5/003 ,  H04L5/0046 ,  H04L5/16 ,  H04L27/2608 ,  H04L27/2647 ,  H04L27/2655 ,  H04L27/34

Abstract: A DMT system for a half-duplex two-way link carries Internet protocol encoded video stream on a coaxial cable that also carries a baseband rendition of the same video stream. A plurality of downlink symbols modulated on a subband of subcarriers in a downlink signal are decoded. The symbols may carry data encoded on a subband using a constellation of QAM symbols assigned to the subband. Other subbands may be associated with different QAM constellations. Lower-order constellations of QAM symbols may be assigned to subbands that include higher-frequency subcarriers and higher-order constellations of QAM symbols may be assigned to subbands that include lower-frequency subcarriers. A block error correction decoder may be synchronized based on an identification of the first constellation of QAM symbols and information identifying boundaries between the plurality of downlink symbols.

公开(公告)号：US20130164896A1

公开(公告)日：2013-06-27

申请号：US13717925

申请日：2012-12-18

Applicant: Intersil Americas Inc.

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: H01L29/66

CPC classification number: H01L27/088

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract translation: 电压转换器包括具有高侧器件的输出电路和可以形成在单个管芯（即“PowerDie”）上并通过半导体衬底相互连接的低侧器件。 高侧器件和低侧器件都可以包括横向扩散的金属氧化物半导体（LDMOS）晶体管。 因为两个输出晶体管都包含相同类型的晶体管，所以可以同时形成两个器件，从而减少超过其它电压转换器设计的光掩模数量。 电压转换器还可以包括在不同的管芯上的控制器电路，其可以与PowerDie电耦合并与其一体化。

公开(公告)号：US20130107133A1

公开(公告)日：2013-05-02

申请号：US13717413

申请日：2012-12-17

Applicant: INTERSIL AMERICAS INC.

Inventor： Daryl Chamberlin ,  Dong Zheng

IPC: H04N5/74

CPC classification number: H04N5/74 ,  G03B21/14 ,  G03B21/28 ,  H04N9/3129 ,  H04N9/3194

Abstract: Embodiments of the present invention generally relate to circuits, systems and methods that can be used to detect light beam misalignment, so that compensation for such misalignment can be performed. In accordance with an embodiment, a circuit includes a photo-detector (PD) having a plurality of electrically isolated PD segments. Additionally, the circuit has circuitry, including switches, configured to control how currents indicative of light detected by the plurality of electrically isolated PD segments are arithmetically combined. When the switches are in a first configuration, a signal produced by the circuitry is indicative of vertical light beam alignment. When the switches are in a second configuration, the signal produced by the circuitry is indicative of horizontal light beam alignment. The signals indicative of vertical light beam alignment and horizontal light beam alignment can be used detect light beam misalignment, so that compensation for such misalignment can be performed.

Abstract translation: 本发明的实施例通常涉及可用于检测光束未对准的电路，系统和方法，从而可以执行对这种不对准的补偿。 根据实施例，电路包括具有多个电隔离PD段的光检测器（PD）。 另外，该电路具有包括开关的电路，其被配置为控制指示由多个电隔离的PD段检测到的光的电流如何被算术组合。 当开关处于第一配置时，由电路产生的信号指示垂直光束对准。 当开关处于第二配置时，由电路产生的信号指示水平光束对准。 可以使用指示垂直光束对准和水平光束对准的信号来检测光束未对准，从而可以执行对这种未对准的补偿。