公开(公告)号：US20100066319A1

公开(公告)日：2010-03-18

申请号：US12501204

申请日：2009-07-10

Applicant: WEIHONG QIU ,  BOGDAN DUDUMAN ,  JASON LIN ,  MICHAEL JASON HOUSTON ,  DOUG MATTINGLY

Inventor： WEIHONG QIU ,  BOGDAN DUDUMAN ,  JASON LIN ,  MICHAEL JASON HOUSTON ,  DOUG MATTINGLY

IPC: G05F1/10

CPC classification number: H02M3/1584

Abstract: A control circuit for generating a control signal to add phases to a multiphase voltage regulator. The control circuit includes an input for receiving an error correction voltage from an error amplifier of the multiphase voltage regulator and at least one output for providing a PWM control signal. Control circuitry generates at least one PWM control signal to add a phase to the multiphase voltage regulator responsive to a determination that the error correction voltage has exceeded a threshold level.

Abstract translation: 一种用于产生控制信号以将相位加到多相电压调节器的控制电路。 控制电路包括用于从多相电压调节器的误差放大器接收误差校正电压的输入端和用于提供PWM控制信号的至少一个输出端。 响应于确定误差校正电压已经超过阈值水平，控制电路产生至少一个PWM控制信号以向多相电压调节器添加相位。

公开(公告)号：USD608505S1

公开(公告)日：2010-01-19

申请号：US29294054

申请日：2007-12-21

Applicant: Jason Lin

Designer： Jason Lin

公开(公告)号：US07499339B2

公开(公告)日：2009-03-03

申请号：US11458431

申请日：2006-07-19

Applicant: Jason Lin

Inventor： Jason Lin

IPC: G11C11/34

CPC classification number: G11C7/1051 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/22 ,  G11C16/10 ,  G11C16/26

Abstract: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe and also a write data strobe that is out-of-phase relative to the read data strobe, and presents data synchronously with one of the edges of that read data strobe. In the advanced mode for a data write, the input data is presented by the controller synchronously with a selected edge of both the write data strobe and the read data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Abstract translation: 公开了一种包括闪速存储器件和控制器的闪速存储器系统，其可根据高级数据传输模式操作。 闪存器件可以在“传统”模式下操作，其中读取数据由存储器与来自控制器的读取数据选通的每个周期同步地呈现，并且其中输入数据由存储器与每个周期同步地锁存 从控制器写入数据选通脉冲。 在控制器将启动命令转发到存储器的高级模式中，闪速存储器本身来源于读取数据选通信号以及相对于读取数据选通信号的异相写入数据选通信号，以及 与读取数据选通的一个边沿同步呈现数据。 在数据写入的高级模式中，输入数据由控制器与写入数据选通和读取数据选通的选定边沿同步呈现。 数据和控制信号的电压摆幅从常规标准中减少，以降低功耗。

公开(公告)号：US07444461B2

公开(公告)日：2008-10-28

申请号：US11499606

申请日：2006-08-04

Applicant: Shai Traister ,  Jason Lin

Inventor： Shai Traister ,  Jason Lin

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7205

Abstract: A method for operating a non-volatile memory storage system is provided. In this method, a write command is received to write data. The write command is allocated a timeout period to complete an execution of the write command. Within the timeout period, a portion of a garbage collection operation is performed. The data associated with the write command are written to a buffer associated with the non-volatile memory storage system.

公开(公告)号：US07299314B2

公开(公告)日：2007-11-20

申请号：US10751096

申请日：2003-12-31

Applicant: Jason Lin ,  Kevin M. Conley ,  Robert C. Chang

Inventor： Jason Lin ,  Kevin M. Conley ,  Robert C. Chang

IPC: G06F12/00

CPC classification number: G11C16/0416 ,  G11C16/10 ,  G11C16/105 ,  G11C2216/16

Abstract: The present invention presents a non-volatile memory and method for its operation that ensures reliable mechanism for write and erase abort detection in the event of lost of power during non-volatile memory programming and erasing with minimized system performance penalty. During a multi-sector write process, an indication of a successful write in one sector is written into the overhead of the following sector at the same time as the following sector's data content is written. The last sector written will additionally have an indication of its own successful write written into its overhead. For erase, an erase abort flag in the first sector of the block can be marked after a successful erase operation.

Abstract translation: 本发明提供了一种用于其操作的非易失性存储器和方法，其确保在非易失性存储器编程和擦除期间由于在最小化的系统性能损失下的擦除而导致的写入和擦除中止检测的可靠机制。 在多扇区写入过程中，在写入下一个扇区的数据内容的同时，在一个扇区中成功写入的指示被写入下一个扇区的开销。 写入的最后一个部分将另外显示自己的成功写入写入其开销。 为了擦除，可以在成功擦除操作之后标记块的第一个扇区中的擦除中止标志。

公开(公告)号：US20070124095A1

公开(公告)日：2007-05-31

申请号：US11622720

申请日：2007-01-12

Applicant: Krishnamurthy Bhaskar ,  Mark Roulo ,  John Taylor ,  Lawrence Miller ,  Paul Russell ,  Jason Lin ,  Eliezer Rosengaus ,  Richard Wallingford ,  Kishore Bubna

Inventor： Krishnamurthy Bhaskar ,  Mark Roulo ,  John Taylor ,  Lawrence Miller ,  Paul Russell ,  Jason Lin ,  Eliezer Rosengaus ,  Richard Wallingford ,  Kishore Bubna

IPC: G01N37/00

CPC classification number: G05B19/41855 ,  G05B2219/37224

Abstract: An inspection system for detecting anomalies on a substrate. The inspection system has a sensor array for generating image data. A first high speed network is coupled to the sensor array and receives and communicates the image data. An array of process nodes is coupled to the first high speed network, and receives and processes the image data to produce anomaly reports. Each process node has an interface card coupled to the first high speed network, that receives the image data from the first high speed network and formats the image data according to a high speed interface bus protocol. The interface card sets a register indicating whether a predetermined amount of image data has been stored in a memory, and the process node reads the register to determine whether the predetermined amount of image data has been stored in the memory, and initiates image processing when the register indicates that the predetermined amount of image data has been stored in the memory.

Abstract translation: 用于检测基板上的异常的检查系统。 检查系统具有用于生成图像数据的传感器阵列。 第一高速网络耦合到传感器阵列并接收并传送图像数据。 一系列过程节点耦合到第一高速网络，并接收和处理图像数据以产生异常报告。 每个处理节点具有耦合到第一高速网络的接口卡，其接收来自第一高速网络的图像数据，并且根据高速接口总线协议格式化图像数据。 接口卡设置表示预定量的图像数据是否已经存储在存储器中的寄存器，并且处理节点读取寄存器以确定预定量的图像数据是否已被存储在存储器中，并且当 寄存器指示预定量的图像数据已被存储在存储器中。

公开(公告)号：US20060233021A1

公开(公告)日：2006-10-19

申请号：US11381998

申请日：2006-05-05

Applicant: Jason Lin ,  Yan Li

Inventor： Jason Lin ,  Yan Li

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

Abstract: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with an erase operation. In the exemplary embodiment, a read operation is inserted just prior to the erase operation or one or more read operations are inserted during a soft programming phase of the erase operation. In this way, the read data could be output while the erase operation is taking place, thereby making use of otherwise waiting time.

Abstract translation: 来自存储器读或写操作的部分延迟是通过I / O总线将数据输入或从存储器的数据锁存器输出。 存在用于通过允许存储器在存储器内核正在进行擦除操作的情况下在后台执行这些数据高速缓存和传送操作中的一些来提高非易失性存储器件中的性能的方法和电路。 在示例性实施例中，在擦除操作之前插入读取操作，或者在擦除操作的软编程阶段插入一个或多个读取操作。 以这种方式，可以在擦除操作发生时输出读取的数据，从而利用另外的等待时间。

公开(公告)号：US20050144362A1

公开(公告)日：2005-06-30

申请号：US10751096

申请日：2003-12-31

Applicant: Jason Lin ,  Kevin Conley ,  Robert Chang

Inventor： Jason Lin ,  Kevin Conley ,  Robert Chang

IPC: G11C16/04 ,  G11C16/10 ,  G06F12/00

CPC classification number: G11C16/0416 ,  G11C16/10 ,  G11C16/105 ,  G11C2216/16

Abstract: The present invention presents a non-volatile memory and method for its operation that ensures reliable mechanism for write and erase abort detection in the event of lost of power during non-volatile memory programming and erasing with minimized system performance penalty. During a multi-sector write process, an indication of a successful write in one sector is written into the overhead of the following sector at the same time as the following sector's data content is written. The last sector written will additionally have an indication of its own successful write written into its overhead. For erase, an erase abort flag in the first sector of the block can be marked after a successful erase operation.

Abstract translation: 本发明提供了一种用于其操作的非易失性存储器和方法，其确保在非易失性存储器编程和擦除期间由于在最小化的系统性能损失下的擦除而导致的写入和擦除中止检测的可靠机制。 在多扇区写入过程中，在写入下一个扇区的数据内容的同时，在一个扇区中成功写入的指示被写入下一个扇区的开销。 写入的最后一个部分将另外显示自己的成功写入写入其开销。 为了擦除，可以在成功擦除操作之后标记块的第一个扇区中的擦除中止标志。