公开(公告)号：US06942514B1

公开(公告)日：2005-09-13

申请号：US10795182

申请日：2004-03-04

Applicant: Tsung-Kan Cheng ,  Tony Chang ,  Forli Wen

Inventor： Tsung-Kan Cheng ,  Tony Chang ,  Forli Wen

IPC: H01R12/18 ,  H01R13/62

CPC classification number: H01R12/721 ,  H01R12/7029 ,  H01R13/6275

Abstract: A connector for electrically connecting a terminal board includes a base having a plurality of contact terminals extending through a rear frame of the base which is received in a case so that the terminal board can be inserted through an elongated hole in the case to contact with the contact terminals. Two release plates extend through two slots defined in two side frames of the base and each has a hook so as to hook respective ones of two recesses of the terminal board. A spring is connected between the two release plates so that when the two release plates are pushed toward each other, the two hooks are disengaged from the recesses of the terminal board and the connector is easily removed from the terminal board.

Abstract translation: 用于电连接端子板的连接器包括具有延伸穿过基座的后框架的多个接触端子的基座，该接触端子容纳在壳体中，使得端子板可以插入壳体中的细长孔以与壳体接触 接触端子。 两个释放板延伸穿过限定在基座的两个侧框架中的两个槽，并且每个隔板具有钩，以钩住端子板的两个凹部中的相应的一个。 弹簧连接在两个释放板之间，使得当两个释放板相互推压时，两个钩与端子板的凹部脱离，并且连接器容易地从端子板移除。

公开(公告)号：USD492686S1

公开(公告)日：2004-07-06

申请号：US29194937

申请日：2003-12-04

Applicant: Gordon Yu ,  Tsung-Kan Cheng ,  Forli Wen

Designer： Gordon Yu ,  Tsung-Kan Cheng ,  Forli Wen

公开(公告)号：US5770911A

公开(公告)日：1998-06-23

申请号：US594011

申请日：1996-01-30

Applicant: Kan Cheng

Inventor： Kan Cheng

IPC: H01L35/00 ,  H01L37/00

CPC classification number: H01L35/00 ,  Y10S136/293

Abstract: A resonant thermoelectric generator includes a thermoelectric power converter connected in series with a resonant circuit. A current generated by the thermoelectric power converter is cycled back and forth in the resonant circuit. The polarity of the thermoelectric power converter with respect to the resonant circuit is switched back and forth to correspond with the direction of the current. In a second embodiment, the thermoelectric power converter is coupled to the resonant circuit through a transformer, and its polarity is also switched to correspond with the direction of the current. In both embodiments, a negative retarding voltage that builds up in the thermoelectric power converter is eliminated by switching its polarity to always correspond with the direction of the current, so that energy is added to the resonant circuit in each cycle, and power is very efficiently converted from heat directly into electricity.

Abstract translation: 谐振热电发电机包括与谐振电路串联连接的热电功率转换器。 由热电功率转换器产生的电流在谐振电路中来回循环。 相对于谐振电路的热电功率转换器的极性来回切换以对应于电流的方向。 在第二实施例中，热电功率转换器通过变压器耦合到谐振电路，并且其极性也被切换以对应于电流的方向。 在两个实施例中，通过将其极性转换为总是对应于电流的方向来消除在热电功率转换器中积累的负延迟电压，使得在每个周期中将能量加到谐振电路上，并且功率非常有效 从热量直接转化为电力。

公开(公告)号：US20210071635A1

公开(公告)日：2021-03-11

申请号：US16563921

申请日：2019-09-08

Applicant: Kan Cheng

Inventor： Kan Cheng

IPC: F03D3/06 ,  F03D7/06 ,  F03D3/00

Abstract: A vertical wind turbine with rotatable wind blades. Under wind pressure, each blade is capable to rotate and stop at a specified location for optimal angle of attack towards the wind to improve the efficiency of the turbine.
Each blade is divided into two unequal area of airfoils with the aerodynamic center of the blade located in the larger area trail end. Under wind pressure, the turbine frame would stop the blades at locations where each blade has an optimal angle of attack towards the wind. As a result, blades in the upwind force zone encounter minimal drag force to improve the efficiency of the turbine.

公开(公告)号：US20190301361A1

公开(公告)日：2019-10-03

申请号：US15937833

申请日：2018-03-27

Applicant: Kan Cheng

Inventor： Kan Cheng

IPC: F02B53/10 ,  F01C21/00 ,  F01C21/04 ,  F02B75/02 ,  F02M23/04 ,  F02D41/00

Abstract: A FAIR engine system includes an air compressor subsystem where oxygen enriched air is compressed, stored and injected into the chambers of a FAIR engine to accelerate the chemical reaction and to reduce harmful mono-nitrogen oxides (NOx) emission

公开(公告)号：US08907441B2

公开(公告)日：2014-12-09

申请号：US12702885

申请日：2010-02-09

Applicant: Huang-Yu Chen ,  Yuan-Te Hou ,  Fung Song Lee ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yi-Kan Cheng ,  Li-Chun Tien ,  Lee-Chung Lu

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Fung Song Lee ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yi-Kan Cheng ,  Li-Chun Tien ,  Lee-Chung Lu

IPC: H01L21/70 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: G06F17/5072 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Abstract translation: 半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。 单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。 在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

公开(公告)号：US08775977B2

公开(公告)日：2014-07-08

申请号：US13027520

申请日：2011-02-15

Applicant: Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

Inventor： Chin-Chang Hsu ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

Abstract translation: 提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。 这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。 标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。 除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层 特征。

公开(公告)号：US08621409B2

公开(公告)日：2013-12-31

申请号：US13459288

申请日：2012-04-30

Applicant: Hui Yu Lee ,  Feng Wei Kuo ,  Ching-Shun Yang ,  Yi-Kan Cheng ,  Jui-Feng Kuan

Inventor： Hui Yu Lee ,  Feng Wei Kuo ,  Ching-Shun Yang ,  Yi-Kan Cheng ,  Jui-Feng Kuan

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5081

Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

Abstract translation: 一种方法包括从半导体电路的第一布局提取第一网表并基于第一网表估计与布局有关的效果数据。 基于使用电子设计自动化工具的第一网表执行半导体电路的第一仿真，并且基于使用电子设计自动化工具的电路示意图来执行半导体电路的第二仿真。 计算至少一个与布局相关的效果的重量和灵敏度，并且基于重量和灵敏度来调整半导体电路的第一布局以提供半导体电路的第二布局。 第二布局存储在非瞬态存储介质中。

公开(公告)号：US08601416B2

公开(公告)日：2013-12-03

申请号：US13535709

申请日：2012-06-28

Applicant: Chin-Cheng Kuo ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Yi-Kan Cheng

Inventor： Chin-Cheng Kuo ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/10

Abstract: A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.

Abstract translation: 一种方法包括（a）产生一组样本，每个样本表示相应的一组半导体制造工艺变化值; （b）基于与每个样本相对应的半导体制造工艺变化值的集合的概率来选择该组样本的第一子集; （c）在不执行蒙特卡罗模拟的情况下，基于所述一组样本和所述第一子集的相对大小来估计半导体产品的屈服度量; 以及（d）如果估计的收益率测量低于规格收益率值，则输出设计修改适当的指示。

公开(公告)号：US08448100B1

公开(公告)日：2013-05-21

申请号：US13444158

申请日：2012-04-11

Applicant: Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

Inventor： Hung Lung Lin ,  Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Yi-Chuin Tsai ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G03F1/70

Abstract: A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.

Abstract translation: 计算机实现的系统包括：编码有表示具有多个多边形的集成电路图案层的初始布局的数据的有形的，非暂时性的计算机可读存储介质。 专用计算机被配置为执行以下步骤：在具有多个多边形的集成电路图案层的初始布局中进行分析，以便在初始布局中识别多个多图案化冲突循环; 在计算机中构建表示每个识别的多图案化冲突周期的相应的多图案化冲突循环图; 根据围绕该多图案化冲突循环图的其他多图案化冲突循环图的数量，在计算机中分类每个识别的多图案化冲突循环图; 并且使得显示装置根据它们各自的分类图形地显示多个多图案化冲突循环图。