公开(公告)号：US20090201063A1

公开(公告)日：2009-08-13

申请号：US12160071

申请日：2006-12-28

Applicant: Masahiro Nomura ,  Yoshifumi Ikenaga ,  Koichi Takeda

Inventor： Masahiro Nomura ,  Yoshifumi Ikenaga ,  Koichi Takeda

IPC: H03K3/289

CPC classification number: H03K3/35625 ,  H03K19/096

Abstract: A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased.

Abstract translation: 动态半导体器件具有多个具有用于临时存储输入数据和动态门部分的开关部分的主步进部分; 多个从步骤部分，与主阶段部分交替地连接并设置有动态门部分或者具有锁存部分和动态门部分; 以及定时信号产生部分，用于产生用于控制主步进部分和从步进部分的操作的信号。 定时信号生成部分在锁存部分提供用于存储数据被擦除之前的前一步骤的数据的信号。

公开(公告)号：US20080251849A1

公开(公告)日：2008-10-16

申请号：US10593300

申请日：2005-03-22

Applicant: Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

Inventor： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

Abstract translation: 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。

公开(公告)号：US07379458B2

公开(公告)日：2008-05-27

申请号：US10115498

申请日：2002-04-03

Applicant: Rumiko Inoue ,  Koichi Takeda

Inventor： Rumiko Inoue ,  Koichi Takeda

IPC: H04L12/56

CPC classification number: H04L61/2517 ,  H04L29/12377 ,  H04L29/12839 ,  H04L61/6022 ,  H04L67/1002 ,  H04L67/1008 ,  H04L67/1017 ,  H04L67/1019 ,  H04L67/1023

Abstract: A server load sharing system having a plurality of server load balancers and a relay device. Each balancer includes a module selecting, any one of a plurality of load sharing target servers specified in their group on the basis of the virtual IP address and each allocated a unique IP address, and a module rewriting a virtual IP address of the received forwarding target packet addressed to the virtual IP address into the unique IP address of the selected server, and rewriting a source IP address of the received packet addressed to the virtual IP address into an IP address capable of specifying the other of the first and second links.

Abstract translation: 一种具有多个服务器负载平衡器和中继装置的服务器负载共享系统。 每个平衡器包括一个模块，根据该虚拟IP地址和每个分配唯一的IP地址，选择在其组中指定的多个负载共享目标服务器中的任何一个，以及重写所接收的转发目标的虚拟IP地址的模块 将寻址到虚拟IP地址的分组转换成所选服务器的唯一IP地址，并将寻址到虚拟IP地址的接收分组的源IP地址重写为能够指定第一和第二链路中的另一个的IP地址。

公开(公告)号：US20080079077A1

公开(公告)日：2008-04-03

申请号：US11570037

申请日：2005-05-25

Applicant: Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

Inventor： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785 ,  Y10S257/903

Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

Abstract translation: 一种具有SRAM单元单元的半导体器件，每个SRAM单元包括一对第一驱动晶体管和第二驱动晶体管，一对第一负载晶体管和第二负载晶体管，以及一对第一存取晶体管和第二存取晶体管，其中 每个晶体管包括从衬底平面向上突出的半导体层，在半导体层的相对侧上延伸以跨越半导体层的顶部的栅极电极，插入在栅极电极和半导体之间的栅极绝缘膜 层，以及形成在半导体层中的一对源极/漏极区域; 并且第一和第二驱动晶体管的沟道宽度均大于至少任一个负载晶体管或每个存取晶体管的沟道宽度。

公开(公告)号：US20070247188A1

公开(公告)日：2007-10-25

申请号：US11628532

申请日：2005-05-25

Applicant: Masahiro Nomura ,  Koichi Takeda

Inventor： Masahiro Nomura ,  Koichi Takeda

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17792

Abstract: A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional repeater unit, arranged between the intersection points of interconnecting unit, performing disconnection, or driving interconnecting unit in the forward direction or in the reverse direction; and interconnection connecting unit, arranged at the intersection point, connecting interconnecting unit at the intersection point.

Abstract translation: 本发明的可编程半导体器件包括：执行预定操作的处理元件单元; 用作信号输入部分的输入/输出连接单元和/或处理元件单元中的信号输出部分; 由多根电线组成的互连单元，经由输入/输出连接单元连接处理元件单元; 双向中继器单元，布置在互连单元的交点之间，在正向或反向上执行断开或驱动互连单元; 和互连连接单元，布置在交点处，交叉点处连接互连单元。

公开(公告)号：US20070075372A1

公开(公告)日：2007-04-05

申请号：US10576412

申请日：2004-10-19

Applicant: Koichi Terashima ,  Kiyoshi Takeuchi ,  shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Atsushi Ogura ,  Koji Watanabe ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka

Inventor： Koichi Terashima ,  Kiyoshi Takeuchi ,  shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Atsushi Ogura ,  Koji Watanabe ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka

IPC: H01L23/62

CPC classification number: H01L29/7853 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device wherein at least the largest width of a source/drain region is larger than the width of a semiconductor region and the source/drain region has a slope having a width continuously increasing from the uppermost side to the substrate side, and a silicide film is formed in the surface of the slope.

Abstract translation: 提供了一种半导体器件，其中源极/漏极区域的至少最大宽度大于半导体区域的宽度，并且源极/漏极区域具有从最上侧到衬底侧的宽度连续增加的斜率， 并且在斜面的表面中形成硅化物膜。

公开(公告)号：US20070041239A1

公开(公告)日：2007-02-22

申请号：US10577398

申请日：2004-09-17

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L27/11

Abstract: The SRAM cells of a semiconductor storage device each comprise first and second inverter circuits loop-connected with each other to form a hold circuit; two access transistors; and a hold control transistor connected in series with a drive transistor of the second inverter circuit. While the memory cell is not accessed, the hold control transistor causes the first and second inverter circuits to form the loop connected hold circuit for statically holding data. When the memory cell is accessed, the hold control transistor causes the first and second inverter circuits to be disconnected from the loop connection for dynamically holding data, thereby preventing data corruption that would otherwise possible occur due to a read operation. Moreover, a sense amplifier circuit that uses a single bit line to read data from a memory cell is disposed in a space appearing in the memory cell array, thereby effectively using the area.

Abstract translation: 半导体存储装置的SRAM单元各自包括彼此环路连接的第一和第二反相器电路，以形成保持电路; 两个存取晶体管; 以及与第二反相器电路的驱动晶体管串联连接的保持控制晶体管。 当存储单元不被访问时，保持控制晶体管使得第一和第二反相器电路形成用于静态保持数据的环路保持电路。 当存储单元被访问时，保持控制晶体管使得第一和第二反相器电路与循环连接断开，用于动态保持数据，从而防止由于读取操作而可能发生的数据损坏。 此外，使用单个位线从存储单元读取数据的读出放大器电路设置在出现在存储单元阵列中的空间中，从而有效地使用该区域。

公开(公告)号：US20060268627A1

公开(公告)日：2006-11-30

申请号：US10570313

申请日：2004-08-27

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C7/10

CPC classification number: G11C11/419

Abstract: There is provided a semiconductor storage device capable of executing a high-speed read operation without increasing a chip area thereof. The semiconductor storage device includes per-bit sensing circuits 103 each connected to a pair of bit lines (BLT, BLN) and a data output circuit 104 connected to the bit lines BLT from the per-bit sensing circuits, for outputting read data. Each of the per-bit sensing circuits 103 includes a pre-charge circuit for setting the bit line pair to a supply voltage VDD when a bit line pair selection signal YS is inactive, a latch circuit for setting the bit line pair to complementary levels (VDD and GND) according to a read signal when the bit line pair selection signal YS and a sensing circuit activation signal SE are active, and a data write circuit connected to a pair of write data lines (WDT, WDN), for setting one of the bit line pair to a second level (GND) according to write data when the bit line pair selection signal is active. The data output circuit 104 includes a logic circuit and an output transistor. The logic circuit outputs a first value when the bit lines are all at a first level (VDD) and outputs a second value when at least one of the bit lines is at the second level. The output transistor outputs read data to a data output line DL based on an output of the logic circuit.

Abstract translation: 提供一种能够在不增加其芯片面积的情况下执行高速读取操作的半导体存储装置。 半导体存储装置包括每位连接到一对位线（BLT，BLN）的每位检测电路103和从每位检测电路连接到位线BLT的数据输出电路104，用于输出读取数据。 每位感测电路103包括用于在位线对选择信号YS无效时将位线对设置为电源电压VDD的预充电电路，用于将位线对设置为互补电平的锁存电路（ VDD和GND），以及与一对写入数据线（WDT，WDN）连接的数据写入电路，用于设置位线对选择信号YS和感测电路激活信号SE之间的读取信号， 当位线对选择信号有效时，根据写入数据，位线对成为第二电平（GND）。 数据输出电路104包括逻辑电路和输出晶体管。 当位线全部处于第一电平（VDD）时，逻辑电路输出第一值，并且当至少一个位线处于第二电平时输出第二值。 输出晶体管基于逻辑电路的输出将读取的数据输出到数据输出线DL。

公开(公告)号：US07073087B2

公开(公告)日：2006-07-04

申请号：US10195458

申请日：2002-07-16

Applicant: Kimito Horie ,  Koichi Takeda

Inventor： Kimito Horie ,  Koichi Takeda

IPC: G06F1/04

CPC classification number: G06F13/28

Abstract: Transition signal control for creating asynchronous timing is provided using a transition signal control circuit, which includes Muller C elements each with an inverter. The control device is constituted by a machine ring including n-stages of transition signal control circuits, a state ring including k-stages of transition signal control circuits, and a synchronous circuit for synchronizing with the machine ring by receiving a vector which is output from the state ring. When the output vector of the state ring is received, the synchronous circuit outputs a vector to the machine ring. The output vector of the machine ring and the output vector of the state ring create timings for controlling the processor, for example, asynchronously, and these timings are input to the instruction decoder, for example.

Abstract translation: 使用过渡信号控制电路提供用于产生异步定时的转换信号控制，该转换信号控制电路包括每个均带有逆变器的Muller C元件。 控制装置由包括n级转换信号控制电路的机械环，包括转换信号控制电路的k级的状态环和用于与机器环同步的同步电路构成，该同步电路通过接收从 国家戒指 当接收到状态环的输出向量时，同步电路向机器环输出一个向量。 例如，机器环的输出向量和状态环的输出向量例如异步地产生用于控制处理器的定时，并且这些定时被输入到指令解码器。

公开(公告)号：US20060134145A1

公开(公告)日：2006-06-22

申请号：US10537462

申请日：2003-12-04

Applicant: Kenji Matsuda ,  Koichi Takeda ,  Toshimitsu Terao ,  Tadaaki Inoue

Inventor： Kenji Matsuda ,  Koichi Takeda ,  Toshimitsu Terao ,  Tadaaki Inoue

IPC: A61K9/00 ,  A61K31/24 ,  A61K31/05

CPC classification number: A61K9/107 ,  A61K9/0019 ,  A61K31/05 ,  A61K47/24

Abstract: The present invention provides a propofol-containing fat emulsion comprising propofol, an oily component, and an emulsifier, and further comprising a predetermined amount of a stabilizer, such as phosphatidylglycerol in which a specific fatty acid is a constituent fatty acid component. The present invention also provides a pain-relieving propofol-containing fat emulsion, which is obtained by mixing a local anaesthetic in advance with the above-described propofol-containing fat emulsion of the invention.

Abstract translation: 本发明提供含有丙泊酚，油性成分和乳化剂的含异丙酚的脂肪乳剂，并且还含有预定量的稳定剂，例如其中特定脂肪酸是构成脂肪酸组分的磷脂酰甘油。 本发明还提供了一种通过将局部麻醉剂预先与本发明的含有异丙酚的脂肪乳剂混合而获得的含有止痛剂的含异丙酚的脂肪乳剂。