摘要:
Imaging system having a sensor array with photocells that permit the monitoring of light levels while the sensor is exposed to a scene, and the ability to accurately avoid saturation on a per column, row, or array basis. The sensor array supports variable dynamic range by allowing variable integration times for different columns or rows of the array, thereby improving image quality of a scene in which there are both strong and weak light areas. In one embodiment, the photocell includes a parasitic multi-emitter bipolar junction transistor (BJT) acting as a photodetector. The parasitic device is part of a saturation detection circuit and also supports an electronic shutter mechanism. The parasitic BJT also permits increased sensitivity over some previous CMOS approaches. The photocell design is also spatially efficient, using in one embodiment only four MOSFETs in addition to the parasitic BJT. The embodiments of the invention are particularly useful in CMOS active pixel sensors used in imaging systems such as the digital camera.
摘要:
A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state.
摘要:
A multi-context register file for use in a multi-threaded processor includes at least one multi-context register file cell having internal routing functionality.
摘要:
An integrated circuit includes power gating circuits for coupling an associated circuit block with a power supply voltage. The power gating circuits also generate power consumption measurements for the associated circuit blocks. A power manager for the integrated circuit may manage the overall power consumption of the integrated circuit and may individually turn on and off the circuit blocks using the power gating circuits.
摘要:
A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.
摘要:
A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal.
摘要:
An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses. The transistors having the thinner gate-oxide may be used to generate data values that may be stored by the transistors having the thicker gate-oxides. The thicker gate-oxides may reduce gate leakage currents during a system standby mode.
摘要:
Imaging system having a sensor array with photocells that permit the monitoring of light levels while the sensor is exposed to a scene, and the ability to accurately avoid saturation on a per column, row, or array basis. The sensor array supports variable dynamic range by allowing variable integration times for different columns or rows of the array, thereby improving image quality of a scene in which there are both strong and weak light areas. In one embodiment, the photocell includes a parasitic multi-emitter bipolar junction transistor (BJT) acting as a photodetector. The parasitic device is part of a saturation detection circuit and also supports an electronic shutter mechanism. The parasitic BJT also permits increased sensitivity over some previous CMOS approaches. The photocell design is also spatially efficient, using in one embodiment only four MOSFETs in addition to the parasitic BJT. The embodiments of the invention are particularly useful in CMOS active pixel sensors used in imaging systems such as the digital camera.
摘要:
Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.