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128 条记录 (耗时 0.031 秒)

    Method and apparatus for dynamic power control of a low power processor
    2.
    发明授权
    Method and apparatus for dynamic power control of a low power processor 有权
    低功率处理器的动态功率控制方法和装置

    公开(公告)号：US06425086B1

    公开(公告)日：2002-07-23

    申请号：US09302560

    申请日：1999-04-30

    申请人： Lawrence T. Clark ,  Bart McDaniel ,  Jay Heeb ,  Tom J. Adelmeyer

    发明人： Lawrence T. Clark ,  Bart McDaniel ,  Jay Heeb ,  Tom J. Adelmeyer

    IPC分类号： G06F132

    CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

    摘要翻译： 简而言之，根据本发明的一个实施例，系统包括：处理器，电压调节器和存储器。 电压调节器耦合到处理器以调整处理器的工作电压。 存储器通过存储器总线耦合到处理器。 存储器已经存储有处理器指令，当处理器执行时，该指令导致处理器的工作频率的修改并且导致处理器的工作电压的调整，至少部分地基于处理器的动态变化 处理器的处理负载。

    Well to substrate photodiode for use in a CMOS sensor on a salicide process
    5.
    发明授权
    Well to substrate photodiode for use in a CMOS sensor on a salicide process 失效
    对于在自对准硅化物工艺中的CMOS传感器中使用的衬底光电二极管

    公开(公告)号：US6040592A

    公开(公告)日：2000-03-21

    申请号：US873987

    申请日：1997-06-12

    申请人： Bart McDaniel ,  Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman ,  Edward J. Bawolek

    发明人： Bart McDaniel ,  Mark A. Beiley ,  Lawrence T. Clark ,  Eric J. Hoffman ,  Edward J. Bawolek

    IPC分类号： H04N1/028 ,  C07D491/048 ,  H01L27/146 ,  H01L31/10 ,  H01L31/113 ,  H01L31/068 ,  H01L31/0352

    CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L31/1136

    摘要： An image sensor having a well-to-substrate diode as the photodetector. In a preferred embodiment, a modern salicided (CMOS) process is utilized to manufacture the image sensor. The field oxide region above the diode junction is transparent to visible light, thus allowing the photodiode competitive quantum efficiency as compared to devices having source/drain diffusion-to-substrate photodiodes fabricated on a non-salicided process. The photodiode can be integrated as part of a sensor array with digital circuitry using a relatively unmodified digital CMOS process. Furthermore, the structure allows the optical properties of the photodiode to be engineered by modifying the well without deleterious effects, to approximate a first order, on the characteristics of a FET built in another identical well.

    摘要翻译： 一种具有良好对衬底二极管作为光电检测器的图像传感器。 在优选实施例中，利用现代的水银（CMOS）工艺来制造图像传感器。 二极管结上方的场氧化物区域对于可见光是透明的，因此与在非水银工艺上制造的源/漏扩散至衬底光电二极管的器件相比，光电二极管的竞争量子效率。 光电二极管可以作为具有使用相对未修改的数字CMOS工艺的数字电路的传感器阵列的一部分进行集成。 此外，该结构允许光电二极管的光学性质通过修改阱而不会对其内置于另一相同阱中的FET的特性产生有害影响，即接近于一阶。

    MULTI-MODE RADIATION HARDENED MULTI-CORE MICROPROCESSORS
    6.
    发明申请
    MULTI-MODE RADIATION HARDENED MULTI-CORE MICROPROCESSORS 审中-公开

    公开(公告)号：US20180046580A1

    公开(公告)日：2018-02-15

    申请号：US15672810

    申请日：2017-08-09

    申请人： Lawrence T. Clark

    发明人： Lawrence T. Clark

    IPC分类号： G06F12/0897

    摘要： Systems and methods for multi-mode radiation hardened multi-core microprocessors are disclosed. In some embodiments, a triplicated circuit includes a first core logic, a second core logic, a third core logic, and bus arbitration and control circuitry. The triplicated circuit is configurable to operate in both a Triple-Modular Redundant (TMR) mode of operation and a multi-threaded mode of operation. In some embodiments, there is essentially no overhead in soft mode and low overhead (power only) in hard mode. In most applications, it is expected that portions of missions require very hard systems (e.g., landing) where a failure is catastrophic. However, other portions require essentially no hardening (digital signal processor and signal processing activities) but much better throughput. Consequently, there is a huge opportunity to develop computer processors with low overhead in soft mode and unprecedented hardness in hard mode.

    RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR
    7.
    发明申请
    RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR 审中-公开
    通过设计微处理器硬化辐射的辐射硬化结构扩展

    公开(公告)号：US20160065243A1

    公开(公告)日：2016-03-03

    申请号：US14837361

    申请日：2015-08-27

    申请人： Dan Wheeler Patterson ,  Lawrence T. Clark

    发明人： Dan Wheeler Patterson ,  Lawrence T. Clark

    IPC分类号： H03M13/11 ,  G06F9/30 ,  H03M13/00

    CPC分类号： G06F9/30145 ,  G06F9/3861 ,  G06F9/3863 ,  G06F11/00

    摘要： This disclosure relates generally to processors and methods of operating the same. In particular, this disclosure relates to components for correcting soft errors in a processor. In one embodiment, a processor includes an instruction decoder and an exception handler. The instruction decoder is configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions. Additionally, an exception handler is configured to execute the one or more soft error correction instructions so as to correct one or more soft errors. In this manner, the processor is capable of correcting soft errors that are the result of radiation strikes.

    摘要翻译： 本公开一般涉及其操作处理器和方法。 特别地，本公开涉及用于校正处理器中的软错误的组件。 在一个实施例中，处理器包括指令解码器和异常处理程序。 指令解码器被配置为接收一个或多个软错误校正指令并对一个或多个软错误校正指令进行解码。 此外，异常处理程序被配置为执行一个或多个软错误校正指令，以便校正一个或多个软错误。 以这种方式，处理器能够校正作为辐射打击结果的软错误。

    Sequential state elements in triple-mode redundant (TMR) state machines
    8.
    发明授权
    Sequential state elements in triple-mode redundant (TMR) state machines 有权
    三模冗余（TMR）状态机中的顺序状态元素

    公开(公告)号：US09038012B2

    公开(公告)日：2015-05-19

    申请号：US14304155

    申请日：2014-06-13

    申请人： Lawrence T. Clark ,  Nathan D. Hindman ,  Dan Wheeler Patterson

    发明人： Lawrence T. Clark ,  Nathan D. Hindman ,  Dan Wheeler Patterson

    IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/003

    CPC分类号： G06F17/5072 ,  G06F17/505 ,  H03K19/00315

    摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

    摘要翻译： 本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。 本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。 位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。 具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。

    Circuit devices and methods having adjustable transistor body bias
    9.
    发明授权
    Circuit devices and methods having adjustable transistor body bias 有权
    具有可调节晶体管体偏置的电路器件和方法

    公开(公告)号：US08995204B2

    公开(公告)日：2015-03-31

    申请号：US13167625

    申请日：2011-06-23

    申请人： Lawrence T. Clark ,  Bruce McWilliams ,  Robert Rogenmoser

    发明人： Lawrence T. Clark ,  Bruce McWilliams ,  Robert Rogenmoser

    IPC分类号： G11C7/00 ,  G11C11/412

    CPC分类号： G11C11/412

    摘要： Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

    摘要翻译： 公开了电路，集成电路器件和方法，其可以包括具有位于栅极下方的屏蔽区域并通过半导体层与栅极分离的可偏置晶体管。 偏置电压可以应用于这样的屏蔽区域以优化多个性能特征，例如速度和电流泄漏。 特定实施例可以包括耦合在高电源电压和低电源电压之间的偏置部分，每个具有可偏置晶体管。 一个或多个发电电路可以产生多个偏置电压。 偏置控制部分可以将不同偏置电压之一耦合到可偏置晶体管的屏蔽区域，以提供用于这种最小速度的最小速度和最小电流泄漏。