公开(公告)号：US20250130937A1

公开(公告)日：2025-04-24

申请号：US18781982

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey

IPC: G06F12/02

Abstract: A system including a memory device and an operatively coupled processing device to perform operations determining a size of a minimum allocation unit (MAU) for a plurality of logical devices, dividing the memory device into logical units with a size equal to the MAU, identifying, using a logical device identifier (LDI) data structure, a first LDI that is available, wherein the first LDI identifies a first logical device, identifying, using a logical unit identifier (LUI) data structure, a first set of LUI that are available, wherein the first set of LUI identify a first set of logical units, allocating the first set of logical units to the first logical device, and updating an LDI-to-LUI mapping data structure to reflect that the first set of logical units are allocated to the first logical device.

公开(公告)号：US20250130878A1

公开(公告)日：2025-04-24

申请号：US18954300

申请日：2024-11-20

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe ,  Aaron P. Boehm

IPC: G06F11/07

Abstract: Methods, systems, and devices for error detection signaling are described. In some examples, a memory device may include circuitry to detect one or more error conditions. As the memory device is operated, it may store or output a value (e.g., a high value, a “1”) indicating the absence of an error condition. Upon the occurrence of an error condition, the memory device may either store or output a value (e.g., a low value, a “0”), which may allow for the error to be corrected or mitigated. Because storing or driving the value signifying the error condition may require a driver of the memory device to be coupled with a power supply, storing or outputting the value signifying an absence of an error condition (e.g., unless a normal or valid condition is detected) may mitigate errors that would otherwise render a safety mechanism of the memory device ineffective.

公开(公告)号：US20250130877A1

公开(公告)日：2025-04-24

申请号：US18790795

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Mark Kalei Hadrick ,  Kang-Yong Kim ,  Donald Morgan ,  Victor Wong

IPC: G06F11/07

Abstract: Apparatuses and techniques for handling faulty usage-based-disturbance data are described. In an example aspect, a memory device uses a report flag to indicate that an address of a row that corresponds to the faulty usage-based-disturbance data is logged at a global-bank level and is accessible by a host device. The report flag also enables the memory device to avoid reporting another error until the host device has cleared information associated with a previously-reported error. In another example aspect, the memory device temporarily prevents usage-based-disturbance mitigation from being performed based on the faulty usage-based-disturbance data. This means that if the faulty usage-based-disturbance data would otherwise trigger refreshing of one or more rows that are proximate to the row corresponding to the faulty usage-based-disturbance data, the memory device does not perform these refresh operations. This is beneficial by conserving resources for refreshing victim rows that are identified based on valid usage-based-disturbance data.

公开(公告)号：US20250130736A1

公开(公告)日：2025-04-24

申请号：US18901899

申请日：2024-09-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Huai-Yuan Tseng ,  David Scott Ebsen

IPC: G06F3/06

Abstract: A processing device in a memory sub-system determines that an amount of host data in a first portion of a memory device configured as a program buffer satisfies a buffer threshold criterion and initiates an initial program pass of first host data from the program buffer to a second portion of the memory device configured as a primary memory. The processing device further determines that the first host data is to be evicted from the program buffer, and initiating a final program pass of the first host data from the program buffer to the primary memory.

公开(公告)号：US20250130718A1

公开(公告)日：2025-04-24

申请号：US18889047

申请日：2024-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Antonino Caprì ,  Graziano Mirichigni ,  Marco Sforzin ,  Bryan David Kerstetter ,  John David Porter

IPC: G06F3/06

Abstract: A system performs operations including: storing a first value in a first memory location used for selecting a sub-channel of a plurality of sub-channels in a communication channel, each of the plurality of sub-channels corresponding to one or more memory components of a plurality of memory components of the memory device, wherein the first value specifies that a sub-channel selecting function is enabled; receiving, through the communication channel, a command directed to the memory device; responsive to receiving the command, storing a second value in a second memory location, wherein the second value is obtained from the command; determining that the second value matches a third value stored in a third memory location, wherein the third value stored in the third memory location comprises a preset value corresponding to a first component of the plurality of components of the memory device; and executing, by the first component, the command.

公开(公告)号：US12284292B2

公开(公告)日：2025-04-22

申请号：US17710591

申请日：2022-03-31

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Alberto Troia

IPC: H04L29/06 ,  H04L9/08 ,  H04L9/32 ,  H04L9/40

Abstract: A method includes receiving, by a computing device, a message from a host device. In response to receiving the message, the computing device generates an identifier, a certificate, and a key. The identifier is associated with an identity of the computing device, and the certificate is generated using the message. The computing device sends the identifier, the certificate, and the key to the host device. The host device verifies the identity of the computing device using the identifier, the certificate, and the key.

公开(公告)号：US12282800B2

公开(公告)日：2025-04-22

申请号：US17075013

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC: G06F9/48 ,  G06F1/10 ,  G06F9/46 ,  G06F9/50 ,  G06F12/0875

Abstract: Devices and techniques for thread replay to preserve state in a barrel processor are described herein. An apparatus includes a barrel processor, which includes a temporary memory; and a thread scheduling circuitry; wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: schedule a current thread to place into a pipeline for the barrel processor on a clock cycle, the barrel processor to schedule threads on each clock cycle; store the current thread in the temporary memory; detect that no thread is available on a clock cycle subsequent to the cycle that the current thread is scheduled; and in response to detecting that no thread is available on the subsequent clock cycle, repeat scheduling the current thread based on the contents of the temporary memory.

公开(公告)号：US12282682B2

公开(公告)日：2025-04-22

申请号：US18415285

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

公开(公告)号：US12282431B2

公开(公告)日：2025-04-22

申请号：US17157303

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz

IPC: G06F12/0866 ,  G06F3/06 ,  G06F12/02

Abstract: Devices and techniques are disclosed herein for implementing, in addition to a first cache, a second, persistent cache in a memory system coupled to a host. The memory system can include flash memory. In certain examples, the first cache and the second cache are configured to store mapping information. In some examples, the mapping information of the second persistent cache is determined by the host using a persistence flag of memory requests provided to the memory system.

公开(公告)号：US20250125266A1

公开(公告)日：2025-04-17

申请号：US18990461

申请日：2024-12-20

Applicant: Micron Technology, Inc.

Inventor： Christopher F. Kinney

IPC: H01L23/528 ,  G11C5/06 ,  H01L23/522

Abstract: Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).