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公开(公告)号：US08902644B2
公开(公告)日：2014-12-02
申请号：US13824888
申请日：2011-12-06
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C2213/74 , G11C2213/79 , H01L43/12
摘要： A magnetoresistive element 10 having a memory cell 100 according to the present invention contains a first lower terminal n1 and a second lower terminal n2 respectively connected to both ends of a conductive layer 3 whose longitudinal direction is different from the column direction (X direction). Further, the gates of the first transistors M1 respectively included in two memory cells among the plurality of memory cells 100 and adjacent to each other in a row direction (Y direction) are commonly connected to a first word line 14. As a result, without increase of the cell area, it becomes possible to reserve a margin in the dimension of the cell structure or in the process for MRMA.
摘要翻译： 具有根据本发明的存储单元100的磁阻元件10包含分别连接到纵向方向不同于列方向（X方向）的导电层3的两端的第一下端子n1和第二下端子n2。 此外，分别包括在多个存储单元100中并且在行方向（Y方向）上彼此相邻的两个存储单元中的第一晶体管M1的栅极共同连接到第一字线14.结果，没有 增加单元面积，可以在单元结构的尺寸或MRMA的处理中保留余量。
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公开(公告)号：US20140233304A1
公开(公告)日：2014-08-21
申请号：US14343325
申请日：2012-09-07
申请人： Ryusuke Nebashi , Noboru Sakimura , Yukihide Tsuji , Ayuka Tada
发明人： Ryusuke Nebashi , Noboru Sakimura , Yukihide Tsuji , Ayuka Tada
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G06F9/30098 , G06F9/30101 , G06F9/4418 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C14/0081 , G11C2207/007 , H03K17/24
摘要： A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.
摘要翻译： 半导体器件包括非易失性寄存器，每个寄存器包括用于以易失性方式保存数据的保持电路和非易失性元件。 一个地址分配给每个非易失性寄存器。 非易失性寄存器控制电路执行控制，使得响应于写指令，保持在保持电路中的数据被写入具有由指令指定的地址的非易失性寄存器中的非易失性元件，并响应于 保持在非易失性元件中的数据的加载指令被保持在具有由指令指定的地址的非易失性寄存器中的保持电路中。
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63.发明授权公开(公告)号：US08354861B2
公开(公告)日：2013-01-15
申请号：US13060574
申请日：2009-08-12
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L43/12 , H03K19/168 , H03K19/18
摘要： A logic gate has a magnetoresistive element, a magnetization state control unit and an output unit. The magnetoresistive element has a laminated structure having N (N is an integer not smaller than 3) magnetic layers and N−1 nonmagnetic layers that are alternately laminated. A resistance value of the magnetoresistive element varies depending on magnetization states of the N magnetic layers. The magnetization state control unit sets the respective magnetization states of the N magnetic layers depending on N input data. The output unit outputs output data that varies depending on the resistance value of the magnetoresistive element.
摘要翻译： 逻辑门具有磁阻元件，磁化状态控制单元和输出单元。 磁阻元件具有交替层叠的N（N为不小于3的整数）磁性层和N-1个非磁性层的叠层结构。 磁阻元件的电阻值根据N个磁性层的磁化状态而变化。 磁化状态控制单元根据N个输入数据来设定N个磁性层的各自的磁化状态。 输出单元输出根据磁阻元件的电阻值而变化的输出数据。
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公开(公告)号：US20120206959A1
公开(公告)日：2012-08-16
申请号：US13433895
申请日：2012-03-29
IPC分类号： G11C11/14
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01L43/08
摘要： A magnetic memory cell 1 is provided with a magnetic recording layer 10 which is a ferromagnetic layer and a pinned layer 30 connected with the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 has a magnetization inversion region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization inversion region 13 has a magnetization whose orientation is invertible and overlaps the pinned layer 30. The first magnetization fixed region 11 is connected with a first boundary B1 in the magnetization inversion region 13 and a magnetization orientation is fixed on a first direction. The second magnetization fixed region 12 is connected with a second boundary B2 in magnetization inversion region 13 and a magnetization orientation is fixed on a second direction. The first direction and the second direction are opposite to each other.
摘要翻译： 磁存储单元1设置有磁记录层10，磁记录层10是铁磁层，和通过非磁性层20与磁记录层10连接的钉扎层30.磁记录层10具有磁化反转区域13， 第一磁化固定区域11和第二磁化固定区域12.磁化反转区域13具有其取向可反转并与被钉扎层30重叠的磁化。第一磁化固定区域11与磁化反转中的第一边界B1连接 区域13和磁化取向在第一方向固定。 第二磁化固定区域12与磁化反转区域13中的第二边界B2连接，并且磁化取向固定在第二方向上。 第一方向和第二方向彼此相反。
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公开(公告)号：US08009466B2
公开(公告)日：2011-08-30
申请号：US12527993
申请日：2008-02-07
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , B82Y10/00 , B82Y25/00 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/228 , H01L43/08
摘要： A semiconductor storage device is provided with a memory array including a plurality of memory cells. The plurality of memory cells includes: first and third memory cells arranged along one of an even-numbered row and an odd-numbered row, and a second memory cell arranged along the other. Each of the plurality of memory cells includes: a first transistor comprising first and second diffusion layers; a second transistor comprising third and fourth diffusion layers; and a magnetoresistance element having one of terminals thereof connected to an interconnection layer which provides an electrical connection between the second and third diffusion layers. The fourth diffusion layer of the first memory cell is also used as the first diffusion layer of the second memory cell. In addition, the fourth diffusion layer of the second memory cell is also used as the first diffusion layer of the third memory cell.
摘要翻译： 半导体存储装置设置有包括多个存储单元的存储器阵列。 多个存储单元包括：沿着偶数行和奇数行中的一个排列的第一和第三存储单元，以及沿着另一列布置的第二存储单元。 多个存储单元中的每一个包括：第一晶体管，包括第一和第二扩散层; 第二晶体管，包括第三和第四扩散层; 以及一个磁阻元件，其一个端子连接到互连层，该互连层提供第二和第三扩散层之间的电连接。 第一存储单元的第四扩散层也用作第二存储单元的第一扩散层。 此外，第二存储单元的第四扩散层也用作第三存储单元的第一扩散层。
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公开(公告)号：US07692956B2
公开(公告)日：2010-04-06
申请号：US12089090
申请日：2006-09-29
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675
摘要： An MRAM is provided with a memory main body (2) having at least one cell array, and a magnetic field detecting section (4) which detects a magnetic field in the vicinity of the memory main body (2) and outputs the detection signal to the memory main body (2). In the cell array, a memory main body (2), which has a plurality of magnetic memory cells including a multilayer ferri-structure as a free layer, stops a prescribed operation of the memory main body (2), based on the detection signal.
摘要翻译： MRAM具有至少一个单元阵列的存储器主体（2）和检测存储器主体（2）附近的磁场的磁场检测部（4），并将检测信号输出到 存储器主体（2）。 在单元阵列中，具有包括多层铁结构的多个磁存储单元作为自由层的存储器主体（2）基于检测信号停止存储器主体（2）的规定的操作 。
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67.发明授权Toggle magnetic random access memory and write method of toggle magnetic random access memory 有权切换磁性随机存取存储器和切换磁性随机存取存储器的写入方法公开(公告)号：US07646628B2
公开(公告)日：2010-01-12
申请号：US11815720
申请日：2006-02-08
IPC分类号： G11C11/00
CPC分类号： G11C7/1027 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693
摘要： A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the first memory array in write wirings used for writing. The controller controls the first memory array and the second memory array such that a first state in which a first burst write operation in the first memory array is executed and a second state in which a second burst write operation in the second memory array is executed are alternately executed in a continuous burst write mode. Accordingly, the continuous burst write operation can be executed at the high speed without any drop in the reliability and any increase in the circuit area.
摘要翻译： 切换磁性随机存取存储器包括第一存储器阵列，第二存储器阵列和控制器。 第一存储器阵列包括多个包括磁阻元件的第一存储单元。 第二存储器阵列包括多个包括磁阻元件的第二存储单元，并且与用于写入的写配线中的第一存储器阵列不同。 控制器控制第一存储器阵列和第二存储器阵列，使得执行第一存储器阵列中的第一突发写入操作的第一状态和其中执行第二存储器阵列中的第二突发写入操作的第二状态是 以连续的突发写入模式交替执行。 因此，可以高速执行连续脉冲串写入操作，而不会降低可靠性和电路面积的任何增加。
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公开(公告)号：US20090125787A1
公开(公告)日：2009-05-14
申请号：US12083373
申请日：2006-10-17
CPC分类号： G11C11/16 , G06F11/1044 , G06F11/1076 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C2029/0411 , G11C2211/5641
摘要： An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits.
摘要翻译： 本发明的MRAM的操作方法存储在存储器阵列中，每个都包括符号，每个符号包括位，并且可以以符号为单位进行纠错。 在操作方法中，通过使用彼此不同的参考单元来读取符号。 此外，当在对应于输入地址的数据单元的错误校正码的读取数据中检测到可校正错误时，（A）对与错误位对应的数据单元中的数据进行校正，对于第一错误符号，作为 一个比特的错误模式和（B）用于读取第二错误符号的参考小区中的数据被校正为第二个错误符号作为比特的错误模式。
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公开(公告)号：US20090122597A1
公开(公告)日：2009-05-14
申请号：US12089090
申请日：2006-09-29
IPC分类号： G11C11/02 , G11C11/14 , G11C11/416
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675
摘要： An MRAM is provided with a memory main body (2) having at least one cell array, and a magnetic field detecting section (4) which detects a magnetic field in the vicinity of the memory main body (2) and outputs the detection signal to the memory main body (2). In the cell array, a memory main body (2), which has a plurality of magnetic memory cells including a multilayer ferri-structure as a free layer, stops a prescribed operation of the memory main body (2), based on the detection signal.
摘要翻译： MRAM具有至少一个单元阵列的存储器主体（2）和检测存储器主体（2）附近的磁场的磁场检测部（4），并将检测信号输出到 存储器主体（2）。 在单元阵列中，具有包括多层铁结构的多个磁存储单元作为自由层的存储器主体（2）基于检测信号停止存储器主体（2）的规定的操作 。
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70.发明申请Toggle Magnetic Random Access Memory and Write Method of Toggle Magnetic Random Access Memory 有权切换磁性随机存取存储器和切换磁性随机存取存储器的写入方法公开(公告)号：US20090010044A1
公开(公告)日：2009-01-08
申请号：US11815720
申请日：2006-02-08
CPC分类号： G11C7/1027 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693
摘要： A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the first memory array in write wirings used for writing. The controller controls the first memory array and the second memory array such that a first state in which a first burst write operation in the first memory array is executed and a second state in which a second burst write operation in the second memory array is executed are alternately executed in a continuous burst write mode. Accordingly, the continuous burst write operation can be executed at the high speed without any drop in the reliability and any increase in the circuit area.
摘要翻译： 切换磁性随机存取存储器包括第一存储器阵列，第二存储器阵列和控制器。 第一存储器阵列包括多个包括磁阻元件的第一存储单元。 第二存储器阵列包括多个包括磁阻元件的第二存储单元，并且与用于写入的写配线中的第一存储器阵列不同。 控制器控制第一存储器阵列和第二存储器阵列，使得执行第一存储器阵列中的第一突发写入操作的第一状态和其中执行第二存储器阵列中的第二突发写入操作的第二状态是 以连续的突发写入模式交替执行。 因此，可以高速执行连续脉冲串写入操作，而不会降低可靠性和电路面积的任何增加。
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