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公开(公告)号：US09135988B2
公开(公告)日：2015-09-15
申请号：US14343325
申请日：2012-09-07
申请人： Ryusuke Nebashi , Noboru Sakimura , Yukihide Tsuji , Ayuka Tada
发明人： Ryusuke Nebashi , Noboru Sakimura , Yukihide Tsuji , Ayuka Tada
CPC分类号： G11C11/419 , G06F9/30098 , G06F9/30101 , G06F9/4418 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C14/0081 , G11C2207/007 , H03K17/24
摘要： A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.
摘要翻译： 半导体器件包括非易失性寄存器，每个寄存器包括用于以易失性方式保存数据的保持电路和非易失性元件。 一个地址分配给每个非易失性寄存器。 非易失性寄存器控制电路执行控制，使得响应于写指令，保持在保持电路中的数据被写入具有由指令指定的地址的非易失性寄存器中的非易失性元件，并响应于 保持在非易失性元件中的数据的加载指令被保持在具有由指令指定的地址的非易失性寄存器中的保持电路中。
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2.发明申请NONVOLATILE RESISTOR NETWORK ASSEMBLY AND NONVOLATILE LOGIC GATE WITH INCREASED FAULT TOLERANCE USING THE SAME 有权非线性电阻网络组件和非易失性逻辑门，使用相同的增加的故障容限公开(公告)号：US20150042376A1
公开(公告)日：2015-02-12
申请号：US14344446
申请日：2012-09-06
IPC分类号： H03K19/177 , G11C11/16
CPC分类号： H03K19/17764 , G11C11/16 , G11C11/1675 , G11C19/0808 , H03K19/1776 , H03K19/18
摘要： Provided is a nonvolatile resistor network assembly characterized by that: it comprises a first and a second resistor network which are each composed of a plurality of nonvolatile resistive elements connected together; it also comprises a write means for writing into the first and second resistor networks; and writing into the first and second resistor networks is performed by the use of the write means in a manner to make total resistances of respectively the first and second resistor networks different from each other. Further provided is a nonvolatile logic gate which performs logical operation using stored data determined by the total resistances of the respective nonvolatile resistor networks.
摘要翻译： 提供了一种非易失性电阻网络组件，其特征在于：它包括第一和第二电阻器网络，每个由连接在一起的多个非易失性电阻元件组成; 它还包括写入第一和第二电阻网络的写入装置; 并且通过使用写入装置以使得第一和第二电阻网络的总电阻彼此不同的方式来执行写入第一和第二电阻器网络的写入。 还提供了一种非易失性逻辑门，其使用由各个非易失性电阻网络的总电阻确定的存储数据执行逻辑运算。
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公开(公告)号：US08737119B2
公开(公告)日：2014-05-27
申请号：US13433895
申请日：2012-03-29
IPC分类号： G11C11/16
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01L43/08
摘要： A magnetic memory cell 1 is provided with a magnetic recording layer 10 which is a ferromagnetic layer and a pinned layer 30 connected with the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 has a magnetization inversion region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization inversion region 13 has a magnetization whose orientation is invertible and overlaps the pinned layer 30. The first magnetization fixed region 11 is connected with a first boundary B1 in the magnetization inversion region 13 and a magnetization orientation is fixed on a first direction. The second magnetization fixed region 12 is connected with a second boundary B2 in magnetization inversion region 13 and a magnetization orientation is fixed on a second direction. The first direction and the second direction are opposite to each other.
摘要翻译： 磁存储单元1设置有磁记录层10，磁记录层10是铁磁层，和通过非磁性层20与磁记录层10连接的钉扎层30.磁记录层10具有磁化反转区域13， 第一磁化固定区域11和第二磁化固定区域12.磁化反转区域13具有其取向可反转并与被钉扎层30重叠的磁化。第一磁化固定区域11与磁化反转中的第一边界B1连接 区域13和磁化取向在第一方向固定。 第二磁化固定区域12与磁化反转区域13中的第二边界B2连接，并且磁化取向固定在第二方向上。 第一方向和第二方向彼此相反。
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公开(公告)号：US08693238B2
公开(公告)日：2014-04-08
申请号：US12376925
申请日：2007-07-13
CPC分类号： G11C8/08 , G11C11/1659 , G11C11/1675
摘要： An MRAM of a spin transfer type is provided with a memory cell 10 and a word driver 30. The memory cell 10 has a magnetic resistance element 1 and a selection transistor TR having one of source/drain electrodes which is connected with one end of the magnetic resistance element 1. The word driver 30 drives a word line WL connected with a gate electrode of the selection transistor TR. The word driver 30 changes a drive voltage of the word line WL according to the write data DW to be written in the magnetic resistance element 1.
摘要翻译： 自旋转移型的MRAM具有存储单元10和字驱动器30.存储单元10具有磁阻元件1和选择晶体管TR，其具有与源极/漏极之一连接的源极/漏极之一 字驱动器30驱动与选择晶体管TR的栅电极连接的字线WL。 字驱动器30根据要写入磁阻元件1的写数据DW改变字线WL的驱动电压。
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公开(公告)号：US08510633B2
公开(公告)日：2013-08-13
申请号：US12596243
申请日：2008-04-14
IPC分类号： G11C29/00
CPC分类号： G11C13/0007 , G06F11/1008 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C29/00 , G11C2013/0054 , G11C2029/0411
摘要： Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 12. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.
摘要翻译： 提供了可应用于PRAM，ReRAM和固体电解质存储器的操作方法，该存储器存储纠错码，每个都包括符号，每个符号包括位，并且哪些代码允许以符号为单位进行纠错 。 在操作方法中，通过使用不同的参考单元12来读取各个符号。当从形成纠错码的数据单元的读取数据中检测到可校正错误并对应于输入地址时，在与数据单元对应的数据单元中的数据 针对一位错误模式的第一错误符号校正错误位，并且对于与多位错误模式相关的第二错误符号来校正用于读取第二错误符号的参考单元中的数据。
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公开(公告)号：US08299830B2
公开(公告)日：2012-10-30
申请号：US12528144
申请日：2008-01-18
IPC分类号： H03L7/00
CPC分类号： G11C13/0011 , G11C11/5614 , G11C13/0069 , G11C27/005 , H03L7/093 , H03L7/10
摘要： A semiconductor device having a nonvolatile variable resistor, includes: a resistance value conversion circuit unit configured to convert a resistance value of the nonvolatile variable resistor into a potential or a current and which outputs the converted potential or current; a comparison circuit unit configured to compare the output from the resistance value conversion circuit unit and a potential or current at a node of a portion within the semiconductor device; and a resistance value changing circuit unit configured to change the resistance value of the nonvolatile variable resistor based on the comparison results from the comparison circuit unit.
摘要翻译： 具有非易失性可变电阻器的半导体器件包括：电阻值转换电路单元，被配置为将所述非易失性可变电阻器的电阻值转换为电位或电流，并输出所述转换的电位或电流; 比较电路单元，被配置为比较来自电阻值转换电路单元的输出和半导体器件内的部分的节点处的电位或电流; 以及电阻值改变电路单元，被配置为基于比较电路单元的比较结果来改变非易失性可变电阻器的电阻值。
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7.发明授权Operation method of MRAM including correcting data for single-bit error and multi-bit error 有权MRAM的操作方法包括纠正单位错误和多位错误的数据公开(公告)号：US08281221B2
公开(公告)日：2012-10-02
申请号：US12083373
申请日：2006-10-17
IPC分类号： G06F11/00
CPC分类号： G11C11/16 , G06F11/1044 , G06F11/1076 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C2029/0411 , G11C2211/5641
摘要： An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits.
摘要翻译： 本发明的MRAM的操作方法存储在存储器阵列中，每个都包括符号，每个符号包括位，并且可以以符号为单位进行纠错。 在操作方法中，通过使用彼此不同的参考单元来读取符号。 此外，当在对应于输入地址的数据单元的错误校正码的读取数据中检测到可校正错误时，（A）对与错误位对应的数据单元中的数据进行校正，对于第一错误符号，作为 一个比特的错误模式和（B）用于读取第二错误符号的参考小区中的数据被校正为第二个错误符号作为比特的错误模式。
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8.发明申请公开(公告)号：US20110148458A1
公开(公告)日：2011-06-23
申请号：US13060574
申请日：2009-08-12
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L43/12 , H03K19/168 , H03K19/18
摘要： A logic gate 40 according to the present invention has a magnetoresistive element 1, a magnetization state control unit 50 and an output unit 60. The magnetoresistive element 1 has a laminated structure having N (N is an integer not smaller than 3) magnetic layers 10 and N−1 nonmagnetic layers that are alternately laminated. A resistance value R of the magnetoresistive element 1 varies depending on magnetization states of the N magnetic layers 10. The magnetization state control unit 50 sets the respective magnetization states of the N magnetic layers 10 depending on N input data. The output unit 60 outputs an output data that varies depending on the resistance value R of the magnetoresistive element 1.
摘要翻译： 根据本发明的逻辑门40具有磁阻元件1，磁化状态控制单元50和输出单元60.磁阻元件1具有N（N是不小于3的整数）磁性层10的层叠结构 和N-1个非磁性层。 磁阻元件1的电阻值R根据N个磁性层10的磁化状态而变化。磁化状态控制单元50根据N个输入数据来设定N个磁性层10的各自的磁化状态。 输出单元60输出根据磁阻元件1的电阻值R而变化的输出数据。
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公开(公告)号：US20110016371A1
公开(公告)日：2011-01-20
申请号：US12596243
申请日：2008-04-14
CPC分类号： G11C13/0007 , G06F11/1008 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C29/00 , G11C2013/0054 , G11C2029/0411
摘要： Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 12. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.
摘要翻译： 提供了可应用于PRAM，ReRAM和固体电解质存储器的操作方法，该存储器存储纠错码，每个都包括符号，每个符号包括位，并且哪些代码允许以符号为单位进行纠错 。 在操作方法中，通过使用不同的参考单元12来读取各个符号。当从形成纠错码的数据单元的读取数据中检测到可校正错误并对应于输入地址时，在与数据单元对应的数据单元中的数据 针对一位错误模式的第一错误符号校正错误位，并且对于与多位错误模式相关的第二错误符号来校正用于读取第二错误符号的参考单元中的数据。
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公开(公告)号：US20090161423A1
公开(公告)日：2009-06-25
申请号：US12066926
申请日：2006-09-07
IPC分类号： G11C11/14 , G11C11/416
CPC分类号： B82Y10/00 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693
摘要： An MRAM having a first cell array group (2-0) and a second cell array group (2-1) containing a plurality of cell arrays (21) is used. Each of the first cell array group (2-0) and the second cell array group (2-1) includes a first current source unit for supplying a first write current IWBL to a bit line WBL of the cell array (21) and a first current waveform shaping unit having a first capacitor requiring precharge and shaping the waveform of the first write current IWBL. When the cell array (21) performs write into a magnetic memory (24), the first current waveform shaping unit of the first cell array group (2-0) and the first current waveform shaping unit of the second cell array group (2-1) charges and discharges electric charge accumulated in the first capacitor to wiring toward the bit line WBL at different periods from each other.
摘要翻译： 使用具有包含多个单元阵列（21）的第一单元阵列组（2-0）和第二单元阵列组（2-1）的MRAM。 第一单元阵列组（2-0）和第二单元阵列组（2-1）中的每一个包括用于将第一写入电流IWBL提供给单元阵列（21）的位线WBL的第一电流源单元和 第一电流波形整形单元，其具有需要预充电的第一电容器并且对第一写入电流IWBL的波形进行整形。 当单元阵列（21）对磁存储器（24）进行写入时，第一单元阵列组（2-0）的第一电流波形整形单元和第二单元阵列组（2- 1）对在第一电容器中累积的电荷进行充电和放电，以不同的周期向位线WBL布线。
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