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公开(公告)号：US08503222B2
公开(公告)日：2013-08-06
申请号：US13144480
申请日：2010-01-21
申请人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
发明人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , H01L43/08 , H03K19/1776 , H03K19/1778 , H03K19/18 , H03K19/20
摘要： A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.
摘要翻译： 非易失性逻辑电路包括输入部分，控制部分和输出部分。 输入部具有垂直的磁各向异性，并具有磁化状态可变的铁磁层。 控制部分包括铁磁层。 输出部分设置在输入部分和控制部分的附近，并且包括磁化状态可变的磁性隧道结元件。 基于磁化状态改变输入部的磁化状态。 输出部分的磁性隧道结元件的磁化状态基于控制部分的铁磁材料的磁化状态和输入部分的铁磁材料的磁化状态而改变。
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公开(公告)号：US08243502B2
公开(公告)日：2012-08-14
申请号：US12747951
申请日：2008-11-19
IPC分类号： G11C11/00
CPC分类号： G11C11/18 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01L27/226 , H01L43/08 , H03K3/45
摘要： A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.
摘要翻译： 非易失性锁存电路包括：锁存电路; 第一磁阻元件和第二磁阻元件; 和电流供应部分。 锁存电路暂时保存数据。 第一磁阻元件和第二磁阻元件中的每一个包括层叠有绝缘膜的第一磁性层和第二磁性层。 电流供应部分基于锁存电路的状态互补地改变第一磁阻元件和第二磁阻元件的磁化状态。 第一磁阻元件的第一磁性层和第二磁阻元件的第一磁性层彼此串联连接。锁存电路具有将对应于磁化状态的数据带入由锁存电路保持的数据的功能。
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公开(公告)号：US20100271866A1
公开(公告)日：2010-10-28
申请号：US12746589
申请日：2008-12-03
CPC分类号： H03K3/45 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/18 , G11C14/0081 , H01L27/11 , H03K3/356008 , Y10S977/933 , Y10S977/935
摘要： A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.
摘要翻译： 非易失性锁存电路包括：交叉耦合以保持1位数据的第一和第二反相器; 第一和第二磁阻元件各自具有第一至第三端子; 以及电流源电路，被配置为响应于1位数据提供用于改变第一和第二电阻元件的磁化状态的磁化反转电流。 第一反相器的电源端子连接到第一磁阻元件的第一端子，第二反相器的电源端子连接到第二磁阻元件的第一端子。 电流供应电路被配置为向第一和第二磁阻元件的第二端提供磁化反转电流。 第一磁阻元件的第三端子电连接到第二磁阻元件的第三端子。
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公开(公告)号：US20100265760A1
公开(公告)日：2010-10-21
申请号：US12747951
申请日：2008-11-19
CPC分类号： G11C11/18 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01L27/226 , H01L43/08 , H03K3/45
摘要： A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.
摘要翻译： 非易失性锁存电路包括：锁存电路; 第一磁阻元件和第二磁阻元件; 和电流供应部分。 锁存电路暂时保存数据。 第一磁阻元件和第二磁阻元件中的每一个包括层叠有绝缘膜的第一磁性层和第二磁性层。 电流供应部分基于锁存电路的状态互补地改变第一磁阻元件和第二磁阻元件的磁化状态。 第一磁阻元件的第一磁性层和第二磁阻元件的第一磁性层彼此串联连接。锁存电路具有将对应于磁化状态的数据带入由锁存电路保持的数据的功能。
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公开(公告)号：US20130182501A1
公开(公告)日：2013-07-18
申请号：US13824888
申请日：2011-12-06
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C2213/74 , G11C2213/79 , H01L43/12
摘要： A magnetoresistive element 10 having a memory cell 100 according to the present invention contains a first lower terminal n1 and a second lower terminal n2 respectively connected to both ends of a conductive layer 3 whose longitudinal direction is different from the column direction (X direction). Further, the gates of the first transistors M1 respectively included in two memory cells among the plurality of memory cells 100 and adjacent to each other in a row direction (Y direction) are commonly connected to a first word line 14. As a result, without increase of the cell area, it becomes possible to reserve a margin in the dimension of the cell structure or in the process for MRMA.
摘要翻译： 具有根据本发明的存储单元100的磁阻元件10包含分别连接到纵向方向不同于列方向（X方向）的导电层3的两端的第一下端子n1和第二下端子n2。 此外，分别包括在多个存储单元100中并且在行方向（Y方向）上彼此相邻的两个存储单元中的第一晶体管M1的栅极共同连接到第一字线14.结果，没有 增加单元面积，可以在单元结构的尺寸或MRMA的处理中保留余量。
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公开(公告)号：US08174872B2
公开(公告)日：2012-05-08
申请号：US12746589
申请日：2008-12-03
IPC分类号： G11C11/00
CPC分类号： H03K3/45 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/18 , G11C14/0081 , H01L27/11 , H03K3/356008 , Y10S977/933 , Y10S977/935
摘要： A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.
摘要翻译： 非易失性锁存电路包括：交叉耦合以保持1位数据的第一和第二反相器; 第一和第二磁阻元件各自具有第一至第三端子; 以及电流源电路，被配置为响应于1位数据提供用于改变第一和第二电阻元件的磁化状态的磁化反转电流。 第一反相器的电源端子连接到第一磁阻元件的第一端子，第二反相器的电源端子连接到第二磁阻元件的第一端子。 电流供应电路被配置为向第一和第二磁阻元件的第二端提供磁化反转电流。 第一磁阻元件的第三端子电连接到第二磁阻元件的第三端子。
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公开(公告)号：US08872542B2
公开(公告)日：2014-10-28
申请号：US13825243
申请日：2011-09-21
IPC分类号： H03K19/177 , G11C13/00 , H03K19/02 , G11C29/02
CPC分类号： H03K19/17748 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0073 , H03K19/02
摘要： A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provided in reconfigurable logic circuit.
摘要翻译： 一种半导体器件包括：可重构逻辑电路，包括多个电阻变化元件; 可重新配置逻辑电路的逻辑配置根据多个电阻变化元件中的每一个是处于第一电阻状态还是在电阻值低于第一电阻状态的电阻值的第二电阻状态决定; 电阻值监视电路，包括预编程到第一电阻状态的电阻变化元件; 检测预编程电阻变化元件是否保持第一电阻状态的电阻值监视电路; 以及控制器，在检测到电阻值监视电路中设置的电阻变化元件未保持第一电阻状态的情况下，将从第二电阻状态到第一电阻状态的编程中使用的电压施加到保持第一电阻状态的电阻变化元件， 设置在可重构逻辑电路中的多个电阻变化元件。
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公开(公告)号：US20130181739A1
公开(公告)日：2013-07-18
申请号：US13825243
申请日：2011-09-21
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0073 , H03K19/02
摘要： A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provided in reconfigurable logic circuit.
摘要翻译： 一种半导体器件包括：包括多个电阻变化元件的可重构逻辑电路; 可重新配置逻辑电路的逻辑配置根据多个电阻变化元件中的每一个是处于第一电阻状态还是在电阻值低于第一电阻状态的电阻值的第二电阻状态决定; 电阻值监视电路，包括预编程到第一电阻状态的电阻变化元件; 检测预编程电阻变化元件是否保持第一电阻状态的电阻值监视电路; 以及控制器，在检测到电阻值监视电路中设置的电阻变化元件未保持第一电阻状态的情况下，将从第二电阻状态到第一电阻状态的编程中使用的电压施加到保持第一电阻状态的电阻变化元件， 设置在可重构逻辑电路中的多个电阻变化元件。
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公开(公告)号：US08284595B2
公开(公告)日：2012-10-09
申请号：US12741299
申请日：2008-10-30
IPC分类号： G11C11/00
CPC分类号： G11C11/1657 , G11C11/1655 , G11C11/1659 , G11C11/1673
摘要： A MRAM includes: first and second bit lines provided to extend in a first direction; a storage block including at least one magnetroresistive element for storing data; and a reading circuit. The reading circuit includes a first terminal electrically connected to the first bit line, and a second terminal electrically connected to the second bit line. The second terminal has a high impedance preventing a steady-state current from flowing into at a time of a reading operation. The reading circuit supplies a reading current from the first terminal to the first bit line at the time of the reading operation. The storage block is configured such that the reading current flows from the first bit line to the magnetroresistive element and the magnetroresistive element is connected to the second bit line at the time of the reading operation. The reading circuit controls the reading current on the basis of a voltage applied to the second terminal through the second bit line.
摘要翻译： MRAM包括：提供为沿第一方向延伸的第一和第二位线; 存储块，其包括用于存储数据的至少一个磁阻元件; 和阅读电路。 读取电路包括电连接到第一位线的第一端子和电连接到第二位线的第二端子。 第二端子具有高阻抗，防止稳态电流在读取操作时流入。 读取电路在读取操作时将读取电流从第一端子提供给第一位线。 存储块被配置为使得读取电流从第一位线流向磁阻元件，并且磁读阻元件在读取操作时连接到第二位线。 读取电路基于通过第二位线施加到第二端子的电压来控制读取电流。
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公开(公告)号：US08009467B2
公开(公告)日：2011-08-30
申请号：US12602230
申请日：2008-04-22
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C15/02 , G11C15/046
摘要： An MRAM according to the present invention has: a memory cell array; a first word line and a second word line each connected to a group of memory cells arranged in a first direction; a plurality of blocks arranged in a matrix form; a common word line connected to a group of blocks arranged in the first direction; and a bit line pair connected to a group of blocks arranged in a second direction. Each block has a plurality of memory cells, and each memory cell has a first transistor and a magnetoresistance element. Each block further has a second transistor to which the plurality of memory cells are connected in parallel. A gate of the second transistor is connected to the common word line. A gate of the first transistor is connected to the first word line. One of source/drain of the first transistor is connected to the first bit line, and the other thereof is connected to one end of the magnetoresistance element and connected to the second bit line through the second transistor. The other end of the magnetoresistance element is connected to the second word line.
摘要翻译： 根据本发明的MRAM具有：存储单元阵列; 每个连接到沿第一方向布置的一组存储器单元的第一字线和第二字线; 以矩阵形式布置的多个块; 连接到沿第一方向布置的块组的公共字线; 以及连接到沿第二方向布置的块组的位线对。 每个块具有多个存储单元，并且每个存储单元具有第一晶体管和磁阻元件。 每个块还具有多个存储单元并联连接的第二晶体管。 第二晶体管的栅极连接到公共字线。 第一晶体管的栅极连接到第一字线。 第一晶体管的源极/漏极之一连接到第一位线，而另一个连接到磁阻元件的一端，并通过第二晶体管连接到第二位线。 磁阻元件的另一端连接到第二字线。
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