公开(公告)号：US07457938B2

公开(公告)日：2008-11-25

申请号：US11240982

申请日：2005-09-30

Applicant: Stephan Jourdan ,  Avinash Sodani ,  Michael Fetterman ,  Per Hammarlund ,  Ronak Singhal ,  Glenn Hinton

Inventor： Stephan Jourdan ,  Avinash Sodani ,  Michael Fetterman ,  Per Hammarlund ,  Ronak Singhal ,  Glenn Hinton

IPC: G06F19/00 ,  G06F15/00 ,  G06F17/00

CPC classification number: G06F9/3001 ,  G06F9/3012 ,  G06F9/3885

Abstract: In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and executing the operation on high order portions of the first and second source operands using a second execution stack of the processor, where the operation in the second execution stack is staggered by one or more cycles from the operation in the first execution stack. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于使用处理器的第一执行堆栈来执行第一和第二源操作数的低阶部分的操作的方法，并且使用第二和第二源操作数对第一和第二源操作数的高阶部分执行操作 处理器的执行堆栈，其中第二执行堆栈中的操作与第一执行堆栈中的操作交错一个或多个周期。 描述和要求保护其他实施例。

公开(公告)号：US07457932B2

公开(公告)日：2008-11-25

申请号：US11323000

申请日：2005-12-30

Applicant: Per Hammarlund ,  Stephan Jourdan ,  Michael Fetterman ,  Glenn Hinton ,  Sebastien Hily ,  Ronak Singhal

Inventor： Per Hammarlund ,  Stephan Jourdan ,  Michael Fetterman ,  Glenn Hinton ,  Sebastien Hily ,  Ronak Singhal

IPC: G06F12/00

CPC classification number: G06F9/30043 ,  G06F9/30032

Abstract: A method is disclosed. The method includes scheduling a load operation at least twice the size of a maximum access supported by a memory device, dividing the load operation into a plurality of separate load operation segments having a size equivalent to the maximum access supported by the memory device, and performing each of the plurality of load operation segments. A further method is disclosed where a temporary register is used to minimize the number of memory accesses to support unaligned accesses.

Abstract translation: 公开了一种方法。 该方法包括将加载操作调度至少是由存储器件支持的最大访问大小的两倍，将加载操作划分成具有等于存储器设备支持的最大访问大小的多个单独的加载操作段，以及执行 多个加载操作段中的每一个。 公开了一种另外的方法，其中使用临时寄存器来最小化用于支持未对齐访问的存储器访问的数量。

公开(公告)号：US20080215861A1

公开(公告)日：2008-09-04

申请号：US12106184

申请日：2008-04-18

Applicant: Tor M. Aamodt ,  Hong Wang ,  Per Hammarlund ,  John P. Shen ,  Steve Shih-wei Liao ,  Perry H. Wang

Inventor： Tor M. Aamodt ,  Hong Wang ,  Per Hammarlund ,  John P. Shen ,  Steve Shih-wei Liao ,  Perry H. Wang

IPC: G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859

Abstract: Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.

Abstract translation: 装置，系统和方法的实施例通过一个或多个推测性线程增强在指令预取期间处理器资源利用的效率。 利用重命名逻辑和映射表来对推测性线程指令流中的指令进行滤波。 映射表包括一个肯定事件位，用于指示相关联的物理寄存器的内容是否反映由主线程计算的值。 线程进度信标表用于跟踪主线程和推测式辅助线程的相对进度。 基于线程进度信标表中的信息，主线程可能会影响不太可能为主线程提供性能优势的辅助线程的终止。

公开(公告)号：US07404065B2

公开(公告)日：2008-07-22

申请号：US11315964

申请日：2005-12-21

Applicant: Stephan Jourdan ,  Per Hammarlund ,  Michael Fetterman ,  Michael P. Cornaby ,  Glenn Hinton ,  Avinash Sodani

Inventor： Stephan Jourdan ,  Per Hammarlund ,  Michael Fetterman ,  Michael P. Cornaby ,  Glenn Hinton ,  Avinash Sodani

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/45

CPC classification number: G06F9/345 ,  G06F9/3017 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3844

Abstract: In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instruction to operate on a vector if the instruction is predicted to be unmasked and unit-stride, the instruction to access elements in memory, and accessing via the optimized μop flow two or more of the elements at the same time without determining masks of the two or more elements. Other embodiments are also described.

Abstract translation: 在一个实施例中，公开了用于向量流单个指令，多数据（SIMD）扩展（VSSE）存储器操作的流优化和预测的方法。 该方法包括：如果预测指令是未屏蔽和单步的，则生成用于对矢量进行操作的指令的优化的微操作（muop）流程，访问存储器中的元件的指令以及经由优化的muop流2访问 或更多的元素，而不确定两个或更多个元件的掩模。 还描述了其它实施例。

公开(公告)号：US07321963B2

公开(公告)日：2008-01-22

申请号：US10773848

申请日：2004-02-05

Applicant: Alan B. Kyker ,  Per Hammarlund ,  Chan Lee ,  Robert F. Krick ,  Hitesh Ahuja ,  William Alexander ,  Joseph Rohlman

Inventor： Alan B. Kyker ,  Per Hammarlund ,  Chan Lee ,  Robert F. Krick ,  Hitesh Ahuja ,  William Alexander ,  Joseph Rohlman

IPC: G06F9/318 ,  G06F9/28

CPC classification number: G06F9/30178 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/30167

Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

公开(公告)号：US20070300049A1

公开(公告)日：2007-12-27

申请号：US11477074

申请日：2006-06-27

Applicant: Avinash Sodani ,  Stephan Jourdan ,  Alexandre Farcy ,  Per Hammarlund

Inventor： Avinash Sodani ,  Stephan Jourdan ,  Alexandre Farcy ,  Per Hammarlund

IPC: G06F9/44

CPC classification number: G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/45504

Abstract: A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than two source values.

Abstract translation: 一种执行三源指令的技术。 本发明的至少一个实施例涉及将三源指令转换成标识不超过两个源值的至少两个指令。

公开(公告)号：US20070239940A1

公开(公告)日：2007-10-11

申请号：US11394914

申请日：2006-03-31

Applicant: Kshitij Doshi ,  Quinn Jacobson ,  Anne Bracy ,  Hong Wang ,  Per Hammarlund

Inventor： Kshitij Doshi ,  Quinn Jacobson ,  Anne Bracy ,  Hong Wang ,  Per Hammarlund

IPC: G06F12/00

CPC classification number: G06F12/0862

Abstract: A technique for adjusting a prefetching rate. More particularly, embodiments of the invention relate to a technique to adjust prefetching as a function of the usefulness of the prefetched data.

Abstract translation: 一种用于调整预取速率的技术。 更具体地，本发明的实施例涉及一种根据预取数据的有用性来调整预取的技术。

公开(公告)号：US20070157006A1

公开(公告)日：2007-07-05

申请号：US11322768

申请日：2005-12-30

Applicant: Stephan Jourdan ,  Avinash Sodani ,  Alexandre Farcy ,  Per Hammarlund ,  Sebastien Hily ,  Mark Davis

Inventor： Stephan Jourdan ,  Avinash Sodani ,  Alexandre Farcy ,  Per Hammarlund ,  Sebastien Hily ,  Mark Davis

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891

Abstract: Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution resources are allocated from a cluster of execution resources that can perform memory access operations but not branching operations. To the other set of micro-operations execution resources are allocated from a cluster of execution resources that can perform branching operations but not memory access operations. The first and second sets of micro-operations may be executed out of sequential order but are retired to represent their sequential instruction ordering.

Abstract translation: 微架构策略和结构分区执行资源集群。 在公开的微架构实施例中，表示顺序指令排序的微操作被划分成两组。 对于一组微操作执行资源从可执行存储器访问操作而不是分支操作的执行资源集群分配。 对另一组微操作执行资源从可执行分支操作而不是存储器访问操作的执行资源集群分配。 第一组和第二组微操作可以按顺序执行，但是退休以表示其顺序指令排序。

公开(公告)号：US07149883B1

公开(公告)日：2006-12-12

申请号：US09539734

申请日：2000-03-30

Applicant: Per Hammarlund ,  Robert Krick

Inventor： Per Hammarlund ,  Robert Krick

IPC: G06F9/00

CPC classification number: G06F9/382 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3814 ,  G06F9/3851

Abstract: A buffer mechanism for buffering microinstructions between a trace cache and an allocator performs a compacting operation by overwriting entries within a queue, known not to store valid instructions or data, with valid instructions or data. Following a write operation to a queue included within the buffer mechanism, pointer logic determines whether the entries to which instructions or data have been written include the valid data or instructions. If an entry is shown to be invalid, the write pointer is not advanced past the relevant entry. In this way, an immediately following write operation will overwrite the invalid data or instruction with data or instruction. The overwriting instruction or data will again be subject to scrutiny (e.g., a qualitative determination) to determine whether it is valid or invalid, and will only be retained within the queue if valid.

Abstract translation: 用于缓冲跟踪高速缓存和分配器之间的微指令的缓冲机制通过覆盖队列中已知不存储有效指令或数据的条目与有效指令或数据来执行压缩操作。 在对缓冲机制中包括的队列进行写入操作之后，指针逻辑确定是否写入了指令或数据的条目包括有效的数据或指令。 如果一个条目显示为无效，则写入指针不会超过相关条目。 以这种方式，紧随其后的写操作将用数据或指令覆盖无效数据或指令。 覆盖指令或数据将再次受到审查（例如，定性确定），以确定其是有效还是无效，并且只有在有效时才会保留在队列中。

公开(公告)号：US07085889B2

公开(公告)日：2006-08-01

申请号：US10104815

申请日：2002-03-22

Applicant: Per Hammarlund ,  Aravindh Baktha ,  Michael D Upton ,  Venkat K. S. Venkatraman

Inventor： Per Hammarlund ,  Aravindh Baktha ,  Michael D Upton ,  Venkat K. S. Venkatraman

IPC: G06F12/00

CPC classification number: G06F12/0842

Abstract: A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.