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公开(公告)号：US08139422B2
公开(公告)日：2012-03-20
申请号：US12494831
申请日：2009-06-30
Applicant: Sang-Jin Byeon
Inventor： Sang-Jin Byeon
IPC: G11C7/00
CPC classification number: G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , H03K19/018521
Abstract: A buffer circuit of a semiconductor memory apparatus includes a compensation voltage generation unit configured to generate a compensation voltage in response to a level of a reference voltage; and a buffering unit configured to generate an output signal by buffering an input signal depending on the reference voltage and control a transition section of the output signal depending on a level of the compensation voltage.
Abstract translation: 半导体存储装置的缓冲电路包括：补偿电压生成单元，被配置为响应于参考电压的电平产生补偿电压; 以及缓冲单元，被配置为通过根据参考电压缓冲输入信号来产生输出信号，并且根据补偿电压的电平来控制输出信号的转换部分。
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公开(公告)号：US08050113B2
公开(公告)日：2011-11-01
申请号：US13023739
申请日：2011-02-09
Applicant: Sang-Jin Byeon
Inventor： Sang-Jin Byeon
CPC classification number: G11C7/04 , G11C5/147 , G11C7/08 , G11C11/4074 , G11C11/4091
Abstract: A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information.
Abstract translation: 核心电压放电器能够根据温度调节放电的电流量。 用于降低预定电压的电平的放电器接收来自管芯热传感器的温度信息，并且响应于温度信息而放电不同量的电流。
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公开(公告)号：US20110221508A1
公开(公告)日：2011-09-15
申请号：US13110669
申请日：2011-05-18
Applicant: Khil-Ohk KANG , Sang-Jin Byeon
Inventor： Khil-Ohk KANG , Sang-Jin Byeon
Abstract: A semiconductor device includes: a first reference voltage generator for generating a first reference voltage; a first band gap circuit for dividing a voltage at a second reference voltage output node to produce a first and a second band gap voltages having a property relative to temperature variations; a first comparator for receiving the first reference voltage as a bias input and comparing the first band gap voltage with the second band gap voltage; and a first driver for pull-up driving the second reference voltage output node in response to an output signal of the first comparator.
Abstract translation: 半导体器件包括：用于产生第一参考电压的第一参考电压发生器; 第一带隙电路，用于分割第二参考电压输出节点处的电压，以产生具有相对于温度变化的性质的第一和第二带隙电压; 第一比较器，用于接收第一参考电压作为偏置输入，并将第一带隙电压与第二带隙电压进行比较; 以及用于响应于第一比较器的输出信号上拉驱动第二参考电压输出节点的第一驱动器。
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公开(公告)号：US20110204950A1
公开(公告)日：2011-08-25
申请号：US12970623
申请日：2010-12-16
Applicant: Jae Bum KO , Jong Chern LEE , Sang Jin BYEON
Inventor： Jae Bum KO , Jong Chern LEE , Sang Jin BYEON
IPC: H03H11/26
CPC classification number: H03K5/1506 , H03K5/05
Abstract: A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.
Abstract translation: 延迟电路包括：延迟单元，被配置为接收时钟信号，按预定时间间隔顺序地延迟输入信号，并输出多个第一延迟信号; 以及选择单元，被配置为基于一个或多个选择信号来选择所述多个第一延迟信号中的一个，并输出第二延迟信号。
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公开(公告)号：US20110187429A1
公开(公告)日：2011-08-04
申请号：US12838332
申请日：2010-07-16
Applicant: Sang Jin BYEON , Jae Jin Lee
Inventor： Sang Jin BYEON , Jae Jin Lee
IPC: H03L7/00
CPC classification number: H03L7/00
Abstract: A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.
Abstract translation: 半导体装置具有堆叠在其中的多个芯片。 用于控制多个芯片的读取操作的读取控制信号与参考时钟同步，使得从应用读取命令到多个芯片中的每一个的数据输出所花费的时间保持基本相同。
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Patent Agency Ranking
公开(公告)号：US07969136B2
公开(公告)日：2011-06-28
申请号：US11987936
申请日：2007-12-06
Applicant: Khil-Ohk Kang , Sang-Jin Byeon
Inventor： Khil-Ohk Kang , Sang-Jin Byeon
IPC: G05F3/30
Abstract: A semiconductor device includes: a first reference voltage generator for generating a first reference voltage; a first band gap circuit for dividing a voltage at a second reference voltage output node to produce a first and a second band gap voltages having a property relative to temperature variations; a first comparator for receiving the first reference voltage as a bias input and comparing the first band gap voltage with the second band gap voltage; and a first driver for pull-up driving the second reference voltage output node in response to an output signal of the first comparator.
Abstract translation: 半导体器件包括：用于产生第一参考电压的第一参考电压发生器; 第一带隙电路，用于分割第二参考电压输出节点处的电压，以产生具有相对于温度变化的性质的第一和第二带隙电压; 第一比较器，用于接收第一参考电压作为偏置输入，并将第一带隙电压与第二带隙电压进行比较; 以及用于响应于第一比较器的输出信号上拉驱动第二参考电压输出节点的第一驱动器。
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公开(公告)号：US20110109382A1
公开(公告)日：2011-05-12
申请号：US12650648
申请日：2009-12-31
Applicant: Sin Hyun JIN , Sang Jin Byeon
Inventor： Sin Hyun JIN , Sang Jin Byeon
IPC: H01L25/00
CPC classification number: G11C5/063 , G11C5/04 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06527 , H01L2225/06541
Abstract: A semiconductor apparatus having a plurality of semiconductor chips is configured in such a manner that the plurality of semiconductor chips share one or more source voltages generated in one of the plurality of semiconductor chips.
Abstract translation: 具有多个半导体芯片的半导体装置被配置为使得多个半导体芯片共享在多个半导体芯片中的一个半导体芯片中生成的一个或多个源极电压。
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公开(公告)号：US07733132B2
公开(公告)日：2010-06-08
申请号：US12082066
申请日：2008-04-07
Applicant: Sang-Jin Byeon
Inventor： Sang-Jin Byeon
IPC: H03K5/153
CPC classification number: G11C7/04 , G11C5/147 , G11C11/4074 , G11C11/4078
Abstract: There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider for generating detection voltage based on an inputted bulk voltage; and a CMOS circuit for generating a output signal having predetermined logic value determined by the detection voltage wherein the voltage divider includes a first transistor having a gate coupled to a ground voltage and a second transistor having a gate coupled to an internal power voltage and a bulk coupled to the inputted bulk voltage.
Abstract translation: 在半导体存储器件中提供体偏置电压VBB电平检测器，其能够通过补偿温度变化来改善在低温下产生的tWR故障。 VBB电平检测器包括半导体存储器件中的体积偏置电压电平检测器，包括：分压器，用于基于输入的体电压产生检测电压; 以及CMOS电路，用于产生具有由检测电压确定的预定逻辑值的输出信号，其中分压器包括具有耦合到接地电压的栅极的第一晶体管和具有耦合到内部电源电压的栅极的第二晶体管， 耦合到输入的体电压。
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公开(公告)号：US20100090721A1
公开(公告)日：2010-04-15
申请号：US12494808
申请日：2009-06-30
Applicant: Sang Jin BYEON
Inventor： Sang Jin BYEON
IPC: H03K19/094 , H03K19/0175
CPC classification number: H03K19/018528
Abstract: A buffer of a semiconductor memory apparatus includes a buffering section configured to generate an output signal by buffering an input signal. A mismatch compensation section generates a control voltage in correspondence with sizes of a second transistor of the same type as a first transistor constituting the buffering section, wherein the buffering section controls a transition time of the output signal in response to a level of the control voltage.
Abstract translation: 半导体存储装置的缓冲器包括：缓冲部，被配置为通过缓冲输入信号来产生输出信号。 不匹配补偿部分根据与构成缓冲部分的第一晶体管相同类型的第二晶体管的尺寸产生控制电压，其中缓冲部分响应于控制电压的电平控制输出信号的转变时间 。
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公开(公告)号：US07468928B2
公开(公告)日：2008-12-23
申请号：US11648283
申请日：2006-12-29
Applicant: Sang Jin Byeon
Inventor： Sang Jin Byeon
IPC: G11C5/14
CPC classification number: G11C5/14
Abstract: An internal voltage generation circuit of a semiconductor memory device controls a dead zone voltage, in which the driving unit that supplies a power supply voltage, does not need to operate. An internal voltage having a dead zone is determined by first and second driving signals based on a level of a reference voltage, and by selectively supplying first and second voltages by means of the first and second driving signals.
Abstract translation: 半导体存储器件的内部电压产生电路控制提供电源电压的驱动单元不需要操作的死区电压。 具有死区的内部电压基于参考电压的电平由第一和第二驱动信号确定，并且通过第一和第二驱动信号选择性地提供第一和第二电压。
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