公开(公告)号：US20120104388A1

公开(公告)日：2012-05-03

申请号：US12970923

申请日：2010-12-16

Applicant: Min Seok CHOI ,  Sang Jin BYEON ,  Young Jun KU

Inventor： Min Seok CHOI ,  Sang Jin BYEON ,  Young Jun KU

IPC: H01L23/58 ,  H01L21/30

CPC classification number: G11C29/806 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: Provided is a 3D stacked semiconductor integrated circuit including a plurality of chips coupled through a plurality of TSVs. A first chip among the plurality of chips is configured to detect and repair a defective TSV among the plurality of TSVs, and transmit repair information to remaining chips other than the first chip, and the remaining chips other than the first chip are configured to repair the defective TSV in response to the repair information.

Abstract translation: 提供了一种3D叠层半导体集成电路，其包括通过多个TSV耦合的多个芯片。 多个芯片中的第一芯片被配置为检测和修复多个TSV之间的缺陷TSV，并将修复信息发送到除第一芯片之外的剩余芯片，并且除第一芯片之外的其余芯片被配置为修复 有缺陷的TSV响应修复信息。

公开(公告)号：US20130241314A1

公开(公告)日：2013-09-19

申请号：US13602257

申请日：2012-09-03

Applicant: Tae Sik YUN ,  Sang Jin BYEON

Inventor： Tae Sik YUN ,  Sang Jin BYEON

IPC: H03K17/00

CPC classification number: H01L25/0657 ,  G01R31/2882 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H03K17/14 ,  H03K19/00369 ,  Y10T307/826

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract translation: 半导体装置包括：从芯片，包括信号传送单元，配置为响应于芯片选择信号确定是否传送输入信号; 包括具有与信号传送单元相同配置的复制电路单元的主芯片和被配置为接收信号传送单元的输出信号和复制电路单元的输出信号的信号输出单元，并响应于 控制信号; 通过垂直形成的从芯片的第一通芯片，并且一端连接到主芯片以接收输入信号，另一端连接到信号传送单元; 以及通过垂直形成的从芯片的第二通芯片，并且其一端连接到信号传送单元，另一端连接到信号输出单元。

公开(公告)号：US20120124408A1

公开(公告)日：2012-05-17

申请号：US13166094

申请日：2011-06-22

Applicant: Sang Jin BYEON ,  Jae Bum Ko

Inventor： Sang Jin BYEON ,  Jae Bum Ko

IPC: G06F1/06 ,  H01L23/498

CPC classification number: G11C5/04 ,  G11C16/20 ,  G11C2029/4402 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/00014

Abstract: A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.

Abstract translation: 半导体装置可以包括：第一芯片ID生成单元，被配置为通过第一穿通硅通孔接收使能信号和通过第二通过硅通孔的时钟信号，并生成第一芯片ID信号和延迟使能信号; 第二芯片ID生成单元，被配置为通过来自第一芯片ID生成单元的第三通过硅通孔和时钟信号接收延迟使能信号，并生成第二芯片ID信号; 第一芯片选择信号生成单元，被配置为接收第一芯片ID信号和主ID信号，并生成第一芯片选择信号; 以及第二芯片选择信号生成单元，被配置为接收第二芯片ID信号和主ID信号，并生成第二芯片选择信号。

公开(公告)号：US20110267137A1

公开(公告)日：2011-11-03

申请号：US12840966

申请日：2010-07-21

Applicant: Jae Bum KO ,  Sang Jin BYEON

Inventor： Jae Bum KO ,  Sang Jin BYEON

IPC: H03K19/003

CPC classification number: H01L25/0657 ,  G11C8/12 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.

Abstract translation: 一种半导体装置，包括单芯片指定码设置块，被配置为生成具有不同码值的多组独立芯片指定码，或者至少两组独立芯片指定码具有 相应的代码值，响应于多个芯片熔丝信号; 控制块，被配置为响应于所述多个芯片熔丝信号和所述多组独立芯片指定代码中的最高有效位而产生多个使能控制信号; 以及单独的芯片激活块，其被配置为响应于所述多个使能控制信号，将所述多个独立芯片指定码组中排除最高有效位的各个芯片指定码与芯片选择地址进行比较，以及 根据比较结果使能多个个别芯片激活信号中的一个。

公开(公告)号：US20100036634A1

公开(公告)日：2010-02-11

申请号：US12478201

申请日：2009-06-04

Applicant: Sang Jin BYEON

Inventor： Sang Jin BYEON

IPC: G01R35/00

CPC classification number: H03K19/00

Abstract: A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time control command, and a calibration clock generating unit configured to output the calibration clock using a code calibration command.

Abstract translation: 一种电阻校准代码生成装置，包括：代码校准单元，被配置为在通过代码校准时间控制命令确定的校准时钟的预定周期期间校准并输出电阻校准代码的代码值;以及校准时钟生成单元， 使用代码校准命令输出校准时钟。

公开(公告)号：US20090140793A1

公开(公告)日：2009-06-04

申请号：US12272944

申请日：2008-11-18

Applicant: Sang Jin BYEON

Inventor： Sang Jin BYEON

IPC: G11C5/14

CPC classification number: G11C5/14

Abstract: An internal voltage generation circuit of a semiconductor memory device controls a dead zone voltage, in which the driving unit that supplies a power supply voltage, does not need to operate. An internal voltage having a dead zone is determined by first and second driving signals based on a level of a reference voltage, and by selectively supplying first and second voltages by means of the first and second driving signals.

Abstract translation: 半导体存储器件的内部电压产生电路控制提供电源电压的驱动单元不需要操作的死区电压。 具有死区的内部电压基于参考电压的电平由第一和第二驱动信号确定，并且通过第一和第二驱动信号选择性地提供第一和第二电压。

公开(公告)号：US20120306566A1

公开(公告)日：2012-12-06

申请号：US13584473

申请日：2012-08-13

Applicant: Sin Hyun JIN ,  Sang Jin BYEON

Inventor： Sin Hyun JIN ,  Sang Jin BYEON

IPC: G05B1/02

CPC classification number: H03K17/22 ,  H01L25/065 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

公开(公告)号：US20120224441A1

公开(公告)日：2012-09-06

申请号：US13171885

申请日：2011-06-29

Applicant: Jae Bum KO ,  Sang Jin BYEON

Inventor： Jae Bum KO ,  Sang Jin BYEON

IPC: G11C7/00

CPC classification number: G11C7/1045 ,  G11C8/10

Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a semiconductor memory apparatus may include a page size control unit configured to generate first and second block enable signals having a level corresponding to one of a plurality of row selection signals or one of a plurality of column selection signals based on a page size control signal; a first page block configured to enable a plurality of first memory cells selected by the plurality of row selection signals in response to the first block enable signal, and activate data access of memory cells selected among the plurality of selected first memory cells by the plurality of column selection signals and the option column selection signal; and a second page block configured to enable a plurality of second memory cells selected by the plurality of row selection signals in response to the second block enable signal, and activate data access of memory cells selected among the plurality of selected second memory cells by the plurality of column selection signals and the option column selection signal.

Abstract translation: 公开了半导体存储装置的各种实施例。 在一个示例性实施例中，半导体存储器设备可以包括页面尺寸控制单元，其被配置为产生具有对应于多个行选择信号中的一个或多个列选择信号中的一个的电平的第一和第二块使能信号， 页面尺寸控制信号; 第一页块，其被配置为响应于所述第一块使能信号使能由所述多个行选择信号选择的多个第一存储器单元，并且激活由所述多个选择的第一存储器单元中选择的多个所选择的第一存储器单元中的多个第一存储器单元的数据访问 列选择信号和选项列选择信号; 以及第二页块，其被配置为响应于所述第二块使能信号使能由所述多个行选择信号选择的多个第二存储器单元，并且激活由所述多个选择的第二存储器单元中选择的所述多个所选择的第二存储器单元中的多个存储单元的数据访问 列选择信号和选项列选择信号。

公开(公告)号：US20110169542A1

公开(公告)日：2011-07-14

申请号：US12839352

申请日：2010-07-19

Applicant: Jae Bum KO ,  Jong Chern LEE ,  Sang Jin BYEON

Inventor： Jae Bum KO ,  Jong Chern LEE ,  Sang Jin BYEON

IPC: H03H11/26

CPC classification number: G11C7/22 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028

Abstract: A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal.

Abstract translation: 半导体存储装置的延迟电路包括：解码单元，被配置为对多个测试信号进行解码并使能多个控制信号中的一个; 偏置电压产生单元，被配置为根据在多个控制信号中使能的控制信号产生第一偏置电压和第二偏置电压; 以及延迟单元，被配置为根据第一和第二偏置电压的电平确定延迟时间，将输入信号延迟所确定的延迟时间，并输出结果信号作为输出信号。

公开(公告)号：US20100097877A1

公开(公告)日：2010-04-22

申请号：US12431981

申请日：2009-04-29

Applicant: Sang Jin BYEON

Inventor： Sang Jin BYEON

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/1045

Abstract: A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal.

Abstract translation: 一种半导体存储装置，包括被配置为由在第一和第二电压节点之间流动的电流驱动的内部电路，以及被配置为响应于操作速度信息信号来控制电流量的电流控制单元。