Abstract:
A fuel cell separator, a fuel cell stack having the fuel cell separator, and a reactant gas control method of the fuel cell stack are provided. That is, even when the fuel cell stack operates under the low load operation condition, a reactant gas is supplied to the reactant gas passages of the fuel cell separator, and thus, the length of the passage can be shortened by 50% as compared with the prior art having only one reactant gas passage. Therefore, the reactant gas can be effectively supplied without experiencing pressure loss. Further, in the high load operation of the fuel cell stack, the reactant gas is introduced into the first reactant gas passage of the fuel cell separator and utilized in half of the whole electrode area. Subsequently, the reactant gas is introduced into the second reactant gas passage and utilized in the remaining half of the electrode area. The flow rate of the reactant gas flowing along the passage channels is increased by two times, even when the reactant gas utilizing rate is identical as compared with the reactant gas flow in the low load operation. As a result, the moisture existing in the passage channels can be more effectively discharged and the flooding phenomenon occurring in the high load operation can be prevented. By controlling the reactant gas supply in accordance with an operation condition of the fuel cell stack without experiencing pressure loss and deterioration of the utilizing rate, the flooding phenomenon and concentration polarization phenomenon that occur in the fuel cell stack can be prevented.
Abstract:
A white organic light emitting device (WOLED) includes electroluminescence (EL) red and blue light emitting layers disposed inside a cavity and a non-electroluminescence (NEL) green light emitting unit disposed outside the cavity or on a region inside the cavity where there are no combinations of electrons and holes. The green light emitting unit adjusts a green spectrum by resonating greenish blue light in the cavity, or is disposed on a path through which red and blue light output from the cavity travels and adapted to absorb the blue light and emit green light. A photoeluminescence (PL) light emitting layer may be a capping layer covering the cavity. The capping layer functions as an optical path control layer controlling an optical path. A white spectrum is obtained by combining blue light and red light generated by EL and green generated by PL. This WOLED can operate at a low voltage.
Abstract:
A spin field effect transistor may include at least one gate electrode, a channel layer, a first stack and a second stack separate from each other on a substrate, wherein the channel layer is formed of a half metal. The half metal may be at least one material selected from the group consisting of chrome oxide (CrO2), magnetite (Fe3O4), a double perovskite structure material, a Heusler alloy, NiMnSb, La(1-x)AxMnO3 (A=Ca, Ba, Sr, x˜0.3), and GaN doped with Cu, and the double perovskite structure material is expressed as a chemical composition of A2BB′O6, and a material corresponding to A is Ca, Sr, or Ba, a material corresponding to B is a 3d orbital transition metal, and a material corresponding to B′ is a 4d orbital transition metal. The 3d orbital transition metal may be Fe or Co, and the 4d orbital transition metal is Mo or Re.
Abstract:
A white organic light emitting device (OLED) includes an anode, a first phosphorescent layer including a first host material and a first dopant disposed on the anode, a blue fluorescence layer including a blue host material and a blue dopant disposed on the first phosphorescent layer, and a second phosphorescent layer including a second host material and a second dopant disposed on the blue fluorescence layer. In addition, a triplet energy of the blue host material of the blue fluorescence layer is greater than both of a triplet energy of the first dopant of the first phosphorescent layer and a triplet energy of the second dopant of the second phosphorescent layer.
Abstract:
Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be erased from the memory transistors by applying an erasing voltage to the bit line or the common source line.
Abstract:
Provided are a memory device, a method of manufacturing the same, and a method of operating the same. The memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected thereinto in a program or erase voltage such that the curved portions into which the charges are injected are separate from a portion which determines a threshold voltage, and a gate structure on the channel region.
Abstract:
A nanowire light emitting device and a method of fabricating the same are provided. The nanowire light emitting device includes a first conductive layer formed on a substrate, a plurality of nanowires vertically formed on the first conductive layer, each of the nanowires having an n-type doped portion and a p-type doped portion, a light emitting layer between the n-type doped portion and the p-type doped portion, first and second conductive organic polymers filling a space corresponding to the p-type doped portion and the n-type doped portion, respectively, and a second conductive layer formed on the nanowires. The organic polymers dope the corresponding surface of the nanowires by receiving electrons from the corresponding surface of the nanowires or by providing electrons to the surface of the nanowires.
Abstract:
Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase operation.
Abstract:
A method of manufacturing a flash memory device which an etch-prevention layer, first and second interlayer insulating layers, and first, second and third hard mask layers are sequentially formed on a semiconductor substrate. The third hard mask layer is etched to expose a portion of a region on the second hard mask layer. A photoresist pattern of a line shape is formed on the entire surface such that the photoresist pattern is exposed to be narrower than the region through which the second hard mask layer is exposed. The second hard mask layer is etched using the photoresist pattern as a mask. The first hard mask layer is etched using the photoresist pattern as a mask, and the second and first interlayer insulating layers are then etched using the remaining third and second hard mask layers as masks, thus forming a drain contact hole having a square shape. The etch-prevention layer is etched using the remaining second and first hard mask layers as masks, thereby exposing a predetermined region of the semiconductor substrate and opening the drain contact hole. It is thus possible to improve a bridge occurring between the contacts.
Abstract:
A method of forming a mask pattern and, more particularly, a method of forming a mask pattern wherein micro patterns having resolutions lower than those of exposure equipment by overcoming the resolutions of the exposure equipment, wherein, a silicon layer is formed over a substrate and is patterned. The patterned silicon layer is oxidized to form the entire surface of the silicon layer to a specific thickness by using an oxide layer. The oxide layer is removed to expose a top surface of the silicon layer. A mask pattern is formed with the remaining oxide layer by removing the silicon layer.