公开(公告)号：US4861683A

公开(公告)日：1989-08-29

申请号：US236350

申请日：1988-08-22

Applicant: Takeshi Nakachi ,  Akio Hata ,  Yoshihisa Watanabe

Inventor： Takeshi Nakachi ,  Akio Hata ,  Yoshihisa Watanabe

IPC: C08F2/06 ,  G11B5/702

CPC classification number: G11B5/7023 ,  Y10S428/90 ,  Y10T428/31797

Abstract: A resin used for magnetic recording media, comprising a vinyl chloride copolymer containing vinyl monomers with hydroxyl groups and vinyl monomers with quaternary ammonium salt groups as component units. The resin is made by a method which comprises polymerizing an organic solvent solution containing vinyl chloride, vinyl monomers with hydroxyl groups and vinyl monomers with quaternary ammonium salt groups in a reacting apparatus to thereby precipitate a vinyl chloride copolymer, the interior surface of said reacting apparatus, which comes into contact with said organic solvent solution being coated with a fluororesin.

公开(公告)号：US4341912A

公开(公告)日：1982-07-27

申请号：US057810

申请日：1979-07-16

Applicant: Kunimasa Takahashi ,  Makoto Imanari ,  Yoshihisa Watanabe

Inventor： Kunimasa Takahashi ,  Makoto Imanari ,  Yoshihisa Watanabe

IPC: B01J23/00 ,  B01J23/44 ,  B01J27/00 ,  B01J27/08 ,  C07B61/00 ,  C07C1/00 ,  C07C5/48 ,  C07C15/44 ,  C07C15/46 ,  C07C67/00 ,  C07C4/02

CPC classification number: B01J27/08 ,  B01J23/44 ,  C07C5/48

Abstract: A process for producing an alkenyl-substituted aromatic compound which comprises catalytically reacting an alkyl-substituted aromatic compound in the vapor phase in the presence of molecular oxygen and a catalyst composed of palladium metal and a metal halide compound supported on an alumina carrier to convert it to the corresponding alkenyl-substituted aromatic compound, wherein said reaction is carried out in the presence of a catalyst composed of palladium metal and a metal halide compound supported on a carrier consisting substantially of .alpha.-alumina.

Abstract translation: 一种制备烯基取代的芳族化合物的方法，其包括在分子氧存在下气相中的烷基取代的芳族化合物和由钯金属和负载在氧化铝载体上的金属卤化物组成的催化剂进行催化反应以将其转化 相应的烯基取代的芳族化合物，其中所述反应在由钯金属和负载在基本上由α-氧化铝组成的载体上的金属卤化物组成的催化剂的存在下进行。

公开(公告)号：US4085193A

公开(公告)日：1978-04-18

申请号：US531304

申请日：1974-12-10

Applicant: Fumito Nakajima ,  Masato Takeuchi ,  Shimpei Matsuda ,  Shigeo Uno ,  Toshikatsu Mori ,  Yoshihisa Watanabe ,  Makoto Imanari

Inventor： Fumito Nakajima ,  Masato Takeuchi ,  Shimpei Matsuda ,  Shigeo Uno ,  Toshikatsu Mori ,  Yoshihisa Watanabe ,  Makoto Imanari

IPC: B01D53/94 ,  B01J23/12 ,  B01J23/22 ,  B01J23/26 ,  B01J23/28 ,  B01J23/30 ,  B01J23/72 ,  B01J23/745 ,  B01J23/75 ,  B01J23/755 ,  B01J23/84 ,  B01J8/00 ,  C01B21/00

CPC classification number: B01J23/84 ,  B01D53/9418 ,  B01J23/12 ,  B01J23/22 ,  B01J23/26 ,  B01J23/28 ,  B01J23/30 ,  B01J23/72 ,  B01J23/745 ,  B01J23/75 ,  B01J23/755 ,  B01D2251/2062 ,  B01D2255/20707 ,  B01D2255/20723 ,  B01D2255/20738 ,  B01D2255/20746 ,  B01D2255/20753 ,  B01D2255/20769 ,  B01D2255/20776 ,  B01D2255/20784

Abstract: A catalyst compositions for reducing nitrogen oxide comprising, as its chief ingredient, an intimate mixture ofA. titanium (Ti) as component A, withB. at least one metal selected from the group consisting of molybdenum (Mo), tungsten (W), iron (Fe), vanadium (V), nickel (Ni), cobalt (Co), copper (Cu), chromium (Cr), and uranium (U), as component B,in the form of their oxides, and a process for reducing nitrogen oxides to nitrogen, which comprises contacting a gaseous mixture containing nitrogen oxides and molecular oxygen and a reducing gas with aforesaid catalyst compositions at an elevated temperature.

Abstract translation: 用于还原氮氧化物的催化剂组合物，其包含作为组分A的A.TiO（Ti）与B的至少一种金属作为其主要成分，所述金属选自钼（Mo），钨（W） ，作为组分B的铁（Fe），钒（V），镍（Ni），钴（Co），铜（Cu），铬（Cr）和铀（U） 将氮氧化物还原成氮的方法，其包括在升高的温度下将含有氮氧化物和分子氧的气态混合物与还原气体与上述催化剂组合物接触。

公开(公告)号：US08791517B2

公开(公告)日：2014-07-29

申请号：US13052152

申请日：2011-03-21

Applicant: Hiroyuki Kutsukake ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

Inventor： Hiroyuki Kutsukake ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

IPC: H01L29/78 ,  H01L29/92

CPC classification number: H01L27/11526 ,  H01L27/11521 ,  H01L27/11529

Abstract: According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.

Abstract translation: 根据一个实施例，半导体器件包括设置在半导体衬底中的至少一个半导体区域和包括设置在半导体区域中的多个电容器的电容器组，每个电容器包括设置在半导体区域上的电容器绝缘膜，电容器 设置在电容器绝缘膜上的电极以及设置在与电容器电极相邻的半导体区域中的至少一个扩散层。

公开(公告)号：US08243517B2

公开(公告)日：2012-08-14

申请号：US12730330

申请日：2010-03-24

Applicant: Makoto Iwai ,  Yoshihisa Watanabe

Inventor： Makoto Iwai ,  Yoshihisa Watanabe

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/26

Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

公开(公告)号：US08213232B2

公开(公告)日：2012-07-03

申请号：US13210431

申请日：2011-08-16

Applicant: Makoto Iwai ,  Yoshihisa Watanabe

Inventor： Makoto Iwai ,  Yoshihisa Watanabe

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/26

Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

Abstract translation: 非易失性半导体存储器包括：存储单元单元，包括具有电荷累积层和控制电极的多个存储单元，所述存储单元串联电连接; 多个字线，其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路，其在数据读出操作期间，从连接到未选择的存储器的未选择的字线的选择时刻开始，选择连接到所述存储单元的所述存储单元的字线的定时。

公开(公告)号：US08199582B2

公开(公告)日：2012-06-12

申请号：US13043624

申请日：2011-03-09

Applicant: Yuka Furuta ,  Yoshihisa Watanabe

Inventor： Yuka Furuta ,  Yoshihisa Watanabe

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.

Abstract translation: 一种控制NAND型闪速存储器的方法，该闪存具有临时存储数据的锁存电路，在锁存电路被保留第一逻辑的第一状态下测量锁存电路的第一消耗电流; 在第二状态下测量锁存电路的第二消耗电流，其中使得所述锁存电路保持通过反转所述第一逻辑而获得的第二逻辑; 以及比较所述第一消耗电流和所述第二消耗电流以使所述锁存电路保持与所述第一消耗电流和所述第二消耗电流中的较小的一个相对应的状态。

公开(公告)号：US20110157994A1

公开(公告)日：2011-06-30

申请号：US13043624

申请日：2011-03-09

Applicant: Yuka FURUTA ,  Yoshihisa Watanabe

Inventor： Yuka FURUTA ,  Yoshihisa Watanabe

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.

Abstract translation: 一种控制NAND型闪速存储器的方法，该闪存具有临时存储数据的锁存电路，在锁存电路被保留第一逻辑的第一状态下测量锁存电路的第一消耗电流; 在第二状态下测量锁存电路的第二消耗电流，其中使得所述锁存电路保持通过反转所述第一逻辑而获得的第二逻辑; 以及比较所述第一消耗电流和所述第二消耗电流以使所述锁存电路保持与所述第一消耗电流和所述第二消耗电流中的较小的一个对应的状态。

公开(公告)号：US20100177563A1

公开(公告)日：2010-07-15

申请号：US12730330

申请日：2010-03-24

Applicant: Makoto Iwai ,  Yoshihisa Watanabe

Inventor： Makoto Iwai ,  Yoshihisa Watanabe

IPC: G11C16/04 ,  G11C16/02

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/26

Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

Abstract translation: 非易失性半导体存储器包括：存储单元单元，包括具有电荷累积层和控制电极的多个存储单元，所述存储单元串联电连接; 多个字线，其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路，其在数据读出操作期间，从连接到未选择的存储器的未选择的字线的选择时刻开始，选择连接到所述存储单元的所述存储单元的字线的定时。

公开(公告)号：US07529131B2

公开(公告)日：2009-05-05

申请号：US11558714

申请日：2006-11-10

Applicant: Makoto Iwai ,  Yoshihisa Watanabe

Inventor： Makoto Iwai ,  Yoshihisa Watanabe

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/26

Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

Abstract translation: 非易失性半导体存储器包括：存储单元单元，包括具有电荷累积层和控制电极的多个存储单元，所述存储单元串联电连接; 多个字线，其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路，其在数据读出操作期间，从连接到未选择的存储器的未选择的字线的选择时刻开始，选择连接到所述存储单元的所述存储单元的字线的定时。