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    Primitive level preemption using discrete non-real-time and real time pipelines
    64.
    发明授权
    Primitive level preemption using discrete non-real-time and real time pipelines 有权

    公开(公告)号：US10210650B1

    公开(公告)日：2019-02-19

    申请号：US15828055

    申请日：2017-11-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Anirudh R. Acharya ,  Swapnil Sakharshete ,  Michael Mantor ,  Mangesh P. Nijasure ,  Todd Martin ,  Vineet Goel

    IPC: G06T15/00 ,  G06T1/20 ,  G06T15/80 ,  G06F9/48 ,  G06F9/50

    Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.

    Method and System for Synchronization of Workitems with Divergent Control Flow
    66.
    发明申请
    Method and System for Synchronization of Workitems with Divergent Control Flow 有权
    工作单元与发散控制流程同步的方法与系统

    公开(公告)号：US20130326524A1

    公开(公告)日：2013-12-05

    申请号：US13672291

    申请日：2012-11-08

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Michael C. HOUSTON ,  Benedict R. Gaster ,  Lee W. Howes ,  Michael Mantor ,  Dominik Behr

    IPC: G06F9/52

    CPC classification number: G06F9/52 ,  G06F9/522

    Abstract: Disclosed methods, systems, and computer program products embodiments include synchronizing a group of workitems on a processor by storing a respective program counter associated with each of the workitems, selecting at least one first workitem from the group for execution, and executing the selected at least one first workitem on the processor. The selecting is based upon the respective stored program counter associated with the at least one first workitem.

    Abstract translation: 公开的方法，系统和计算机程序产品实施例包括通过存储与每个工作项相关联的相应程序计数器来同步处理器上的一组工作项，从组中选择至少一个第一工作以供执行，以及执行所选择的至少 处理器上的第一个工作。 所述选择基于与所述至少一个第一工作项相关联的相应存储的程序计数器。

    Reconfigurable virtual graphics and compute processor pipeline
    67.
    发明授权
    Reconfigurable virtual graphics and compute processor pipeline 有权

    公开(公告)号：US12254527B2

    公开(公告)日：2025-03-18

    申请号：US16879991

    申请日：2020-05-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Timour T. Paltashev ,  Michael Mantor ,  Rex Eldon McCrary

    IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/80 ,  G06T17/10

    Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.

    MULTIMODAL CONTEXTUALIZER FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION
    68.
    发明申请
    MULTIMODAL CONTEXTUALIZER FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION 有权

    公开(公告)号：US20240428494A1

    公开(公告)日：2024-12-26

    申请号：US18749032

    申请日：2024-06-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Karthik Mohan Kumar ,  Michael Mantor ,  Pedro Antonio Pena ,  Archana Ramalingam

    IPC: G06T13/40 ,  H04N19/124

    Abstract: Systems and techniques for generating and animating non-player characters (NPCs) within virtual digital environments are provided. Multimodal input data is received that comprises a plurality of input modalities for interaction with an NPC having a set of body features and a set of facial features. The multimodal input data is processed through one or more neural networks to generate animation sequences for both the body features and facial features of the NPC. Generating such animation sequences includes disentangling the multimodal input data to generate substantially disentangled latent representations, combining these representations with the multimodal input data, and using a large-language model (LLM) to generate speech data for the NPC. Further processing using reverse diffusion generates face vertex displacement data and joint trajectory data based on the combined representation and generated speech data. The face vertex displacement data, joint trajectory data, and speech data are used to produce an animated representation of the NPC, which is then provided to environment-specific adapters to animate the NPC within a virtual digital environment.

    Hierarchical work scheduling
    69.
    发明授权
    Hierarchical work scheduling 有权

    公开(公告)号：US12153957B2

    公开(公告)日：2024-11-26

    申请号：US17957714

    申请日：2022-09-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

    IPC: G06F9/48

    Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

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