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    RECONFIGURABLE VIRTUAL GRAPHICS AND COMPUTE PROCESSOR PIPELINE
    3.
    发明申请
    RECONFIGURABLE VIRTUAL GRAPHICS AND COMPUTE PROCESSOR PIPELINE 审中-公开

    公开(公告)号：US20180114290A1

    公开(公告)日：2018-04-26

    申请号：US15331278

    申请日：2016-10-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Timour T. Paltashev ,  Michael Mantor ,  Rex Eldon McCrary

    IPC: G06T1/20 ,  G06T1/60

    Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.

    Culling objects from a 3-D graphics pipeline using hierarchical Z buffers
    4.
    发明授权
    Culling objects from a 3-D graphics pipeline using hierarchical Z buffers 有权

    公开(公告)号：US10032308B2

    公开(公告)日：2018-07-24

    申请号：US15189656

    申请日：2016-06-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Timour T. Paltashev ,  Chris Brennan

    IPC: G06T15/40 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

    Abstract: A shader in a graphics pipeline accesses an object that represents a portion of a model of a scene in object space and one or more far-z values that indicate a furthest distance of a previously rendered portion of one or more tiles from a viewpoint used to render the scene on a screen. The one or more tiles overlap a bounding box of the object in a plane of the screen. The shader culls the object from the graphics pipeline in response to the one or more far-z values being smaller than a near-z value that represents a closest distance of a portion of the object to the viewpoint.

    Reconfigurable virtual graphics and compute processor pipeline
    7.
    发明授权
    Reconfigurable virtual graphics and compute processor pipeline 有权

    公开(公告)号：US12254527B2

    公开(公告)日：2025-03-18

    申请号：US16879991

    申请日：2020-05-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Timour T. Paltashev ,  Michael Mantor ,  Rex Eldon McCrary

    IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/80 ,  G06T17/10

    Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.

    PARALLEL MICROPOLYGON RASTERIZERS
    8.
    发明申请
    PARALLEL MICROPOLYGON RASTERIZERS 审中-公开

    公开(公告)号：US20180061124A1

    公开(公告)日：2018-03-01

    申请号：US15251914

    申请日：2016-08-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Boris Prokopenko ,  Timour T. Paltashev ,  Vladimir V. Kibardin

    IPC: G06T17/20 ,  G06T15/00 ,  G06T17/10

    CPC classification number: G06T17/20 ,  G06T15/005 ,  G06T17/10 ,  G06T2210/12

    Abstract: A parallel adaptable graphics rasterization system in which a primitive assembler includes a router to selectively route a primitive to a first rasterizer or one of a plurality of second rasterizers. The second rasterizers concurrently operate on different primitives and the primitive is selectively routed based on an area of the primitive. In some variations, a bounding box of the primitive is reduced to a predetermined number of pixels prior to providing the primitive to the one of the plurality of second rasterizers. Reducing the bounding box can include subtracting an origin of the bounding box from coordinates of points that represent the primitive.

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