公开(公告)号：US11462630B2

公开(公告)日：2022-10-04

申请号：US16640580

申请日：2018-08-28

Applicant: Applied Materials, Inc.

Inventor： Rui Cheng ,  Yi Yang ,  Karthik Janakiraman ,  Abhijit Basu Mallick

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments described herein generally relate to doping of three dimensional (3D) structures on a substrate. In some embodiments, a conformal dopant containing film may be deposited over the 3D structures. Suitable dopants that may be incorporated in the film include halogen atoms. The film may be subsequently annealed to diffuse the dopants into the 3D structures.

公开(公告)号：US20220199373A1

公开(公告)日：2022-06-23

申请号：US17127201

申请日：2020-12-18

Applicant: Applied Materials, Inc.

Inventor： Venkata Sharat Chandra Parimi ,  Zubin Huang ,  Manjunath Veerappa Chobari Patil ,  Nitin Pathak ,  Yi Yang ,  Badri N. Ramamurthi ,  Truong Van Nguyen ,  Rui Cheng ,  Diwakar Kedlaya

IPC: H01J37/32 ,  C23C16/50 ,  C23C16/458 ,  C23C16/44

Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.

公开(公告)号：US11335555B2

公开(公告)日：2022-05-17

申请号：US17045323

申请日：2019-04-05

Applicant: Applied Materials, Inc.

Inventor： Rui Cheng ,  Yi Yang ,  Karthik Janakiraman

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L21/225

Abstract: Methods of conformally doping three dimensional structures are discussed. Some embodiments utilize conformal silicon films deposited on the structures. The silicon films are doped after deposition to comprise halogen atoms. The structures are then annealed to dope the structures with halogen atoms from the doped silicon films.

公开(公告)号：US20220108892A1

公开(公告)日：2022-04-07

申请号：US17063339

申请日：2020-10-05

Applicant: Applied Materials, Inc.

Inventor： Yi Yang ,  Krishna Nittala ,  Rui Cheng ,  Karthik Janakiraman ,  Diwakar Kedlaya ,  Zubin Huang ,  Aykut Aydin

IPC: H01L21/033 ,  C23C16/38

Abstract: Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H2) into the substrate processing region of the semiconductor processing chamber. The boron-containing precursor and the H2 may be flowed at a boron-to-hydrogen flow rate ratio. The flow rate of the boron-containing precursor and the H2 may be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. The boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.

公开(公告)号：US11236418B2

公开(公告)日：2022-02-01

申请号：US16853689

申请日：2020-04-20

Applicant: Applied Materials, Inc.

Inventor： Rui Cheng ,  Abhijit Basu Mallick ,  Pramit Manna

IPC: H01L21/02 ,  C23C16/24 ,  C23C16/04 ,  C23C16/40 ,  C23C16/34 ,  C23C16/56 ,  H01L21/762

Abstract: Methods for gapfill of high aspect ratio features are described. A first film is deposited on the bottom and upper sidewalls of a feature. The first film is etched from the sidewalls of the feature and the first film in the bottom of the feature is treated to form a second film. The deposition, etch and treat processes are repeated to fill the feature.

公开(公告)号：US20200335334A1

公开(公告)日：2020-10-22

申请号：US16754619

申请日：2018-10-09

Applicant: Applied Materials, Inc.

Inventor： Rui Cheng ,  Yihong Chen ,  Yong Wu ,  Abhijit Basu Mallick ,  Srinivas Gandikota

IPC: H01L21/02 ,  H01L21/285

Abstract: Methods for depositing a metal film on a doped amorphous silicon layer as a nucleation layer and/or a glue layer on a substrate. Some embodiments further comprise the incorporation of a glue layer to increase the ability of the doped amorphous silicon layer and metal layer to stick to the substrate.

公开(公告)号：US10811303B2

公开(公告)日：2020-10-20

申请号：US16259175

申请日：2019-01-28

Applicant: Applied Materials, Inc.

Inventor： Pramit Manna ,  Ludovic Godet ,  Rui Cheng ,  Erica Chen ,  Ziqing Duan ,  Abhijit Basu Mallick ,  Srinivas Gandikota

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/768 ,  H01L23/31 ,  H01L29/06

Abstract: Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).

公开(公告)号：US10699903B2

公开(公告)日：2020-06-30

申请号：US16659194

申请日：2019-10-21

Applicant: Applied Materials, Inc.

Inventor： Pramit Manna ,  Shishi Jiang ,  Rui Cheng ,  Abhijit Basu Mallick

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber. A conformal deposition process is then performed to deposit a conformal silicon liner layer on the sidewalls of the features and the exposed first surface of the substrate between the features. A flowable deposition process is then performed to deposit a flowable silicon layer over the conformal silicon liner layer. A curing process is then performed to increase silicon density of the flowable silicon layer. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition two-step process to realize seam-free gapfilling between features with high quality amorphous silicon film.

公开(公告)号：US20190326123A1

公开(公告)日：2019-10-24

申请号：US16435910

申请日：2019-06-10

Applicant: Applied Materials, Inc.

Inventor： Zihui Li ,  Rui Cheng ,  Anchuan Wang ,  Nitin K. Ingle ,  Abhijit Basu Mallick

IPC: H01L21/3065

Abstract: Exemplary methods for selectively removing silicon (e.g. polysilicon) from a patterned substrate may include flowing a fluorine-containing precursor into a substrate processing chamber to form plasma effluents. The plasma effluents may remove silicon (e.g. polysilicon, amorphous silicon or single crystal silicon) at significantly higher etch rates compared to exposed silicon oxide, silicon nitride or other dielectrics on the substrate. The methods rely on the temperature of the substrate in combination with some conductivity of the surface to catalyze the etch reaction rather than relying on a gas phase source of energy such as a plasma.

公开(公告)号：US10319600B1

公开(公告)日：2019-06-11

申请号：US15918860

申请日：2018-03-12

Applicant: Applied Materials, Inc.

Inventor： Zihui Li ,  Rui Cheng ,  Anchuan Wang ,  Nitin K. Ingle ,  Abhijit Basu Mallick

IPC: H01L21/3065 ,  H01L21/311

Abstract: Exemplary methods for selectively removing silicon (e.g. polysilicon) from a patterned substrate may include flowing a fluorine-containing precursor into a substrate processing chamber to form plasma effluents. The plasma effluents may remove silicon (e.g. polysilicon, amorphous silicon or single crystal silicon) at significantly higher etch rates compared to exposed silicon oxide, silicon nitride or other dielectrics on the substrate. The methods rely on the temperature of the substrate in combination with some conductivity of the surface to catalyze the etch reaction rather than relying on a gas phase source of energy such as a plasma.