公开(公告)号：US11366779B2

公开(公告)日：2022-06-21

申请号：US16685090

申请日：2019-11-15

Applicant: Arm Limited ,  ECS Partners Limited

Inventor： Benjamin James Fletcher ,  James Edward Myers ,  Shidhartha Das ,  Terrence Sui Tung Mak

IPC: G06F13/40 ,  H04L12/40

Abstract: A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.

公开(公告)号：US20220164511A1

公开(公告)日：2022-05-26

申请号：US17218670

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Zhiyao Xie ,  Shidhartha Das ,  Matthew James Walker ,  Kumara Guru Palaniswamy ,  Matthew Paul Elwood

IPC: G06F30/367 ,  G01R21/133 ,  G01R31/317

Abstract: A power meter for measuring power usage in a circuit includes preprocessor and a weighting network. The pre-processor is configured to receive toggle data for a number of power proxy signals in the circuit for a plurality of clock cycles of the circuit in a first time window. The power proxy signals and weighting values are determined automatically from simulated or emulated toggle data. For each power proxy signal, the pre-processor averages the toggle data over one or more clock cycles in one or more second time windows, within the first time window, to provide averaged toggle data, and outputs the averaged toggle data for each second time window. The weighting network is configured to combine the averaged toggle data from the power proxy signals, based on a set of weight values, to provide a measure of the power usage.

公开(公告)号：US20220101085A1

公开(公告)日：2022-03-31

申请号：US17036490

申请日：2020-09-29

Applicant: Arm Limited

Inventor： Fernando Garcia Redondo ,  Shidhartha Das ,  Paul Nicholas Whatmough ,  Glen Arnold Rosendale

IPC: G06N3/04 ,  G11C13/00 ,  G06F7/544

Abstract: A non-volatile memory (NVM) crossbar for an artificial neural network (ANN) accelerator is provided. The NVM crossbar includes row signal lines configured to receive input analog voltage signals, multiply-and-accumulate (MAC) column signal lines, a correction column signal line, a MAC cell disposed at each row signal line and MAC column signal line intersection, and a correction cell disposed at each row signal line and correction column signal line intersection. Each MAC cell includes one or more programmable NVM elements programmed to an ANN unipolar weight, and each correction cell includes one or more programmable NVM elements. Each MAC column signal line generates a MAC signal based on the input analog voltage signals and the respective MAC cells, and the correction column signal line generates a correction signal based on the input analog voltage signals and the correction cells. Each MAC signal is corrected based on the correction signal.

公开(公告)号：US11061852B2

公开(公告)日：2021-07-13

申请号：US16645993

申请日：2018-09-25

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Emre Ozer ,  Xabier Iturbe ,  Shidhartha Das

IPC: G11C7/00 ,  G06F15/78 ,  G11C14/00 ,  H03K19/17728 ,  G06F15/76

Abstract: A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

公开(公告)号：US20210150071A1

公开(公告)日：2021-05-20

申请号：US17048502

申请日：2019-04-18

Applicant: Arm Limited

Inventor： Hugo John Martin Vincent ,  Shidhartha Das ,  Milosch Meriac ,  Vasileios Tenentes

IPC: G06F21/75 ,  H04L9/00 ,  G01R19/00 ,  G01R19/165 ,  G01R29/26

Abstract: An apparatus and method for detecting a change in electrical properties in a system is disclosed. Embodiments of the disclosure enable the detection of a change in electrical properties in a system by, in response to a load generated on a power delivery network power in at least part of the system, measuring noise induced in the power delivery network in response to the load. Based on the measured noise, a dynamic-response property of the power delivery network is determined and the dynamic-response property is compared to a stored reference dynamic-response property of the power delivery network based on a predetermined load. In the event of a difference between the dynamic-response property and the reference dynamic-response property, a response to the event is triggered to indicate tampering with the power delivery network.

公开(公告)号：US11004479B2

公开(公告)日：2021-05-11

申请号：US16833154

申请日：2020-03-27

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Shidhartha Das ,  George McNeil Lattimore ,  Brian Tracy Cline

IPC: G11C5/06 ,  G11C14/00 ,  G11C8/10 ,  G11C13/00

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

公开(公告)号：US20210097207A1

公开(公告)日：2021-04-01

申请号：US17048530

申请日：2019-04-18

Applicant: Arm Limited

Inventor： Milosch Meriac ,  Hugo John Martin Vincent ,  Shidhartha Das ,  Vasileios Tenentes

IPC: G06F21/75 ,  H04L9/00 ,  H04L9/32 ,  G01R19/165

Abstract: An apparatus and system for remote attestation of a power delivery network is disclosed. Embodiments of the disclosure enable remote attestation of the power delivery network by storing a trusted golden reference waveform in secure memory. The trusted golden reference waveform characterizes a power delivery network in response to a load generated on the power delivery network. A remote cloud server generates a server-generated remote attestation of the power delivery network by receiving an attestation packet from the power delivery network and verifying whether the attestation packet is consistent with an expected power delivery network identity.

公开(公告)号：US20210090653A1

公开(公告)日：2021-03-25

申请号：US16582743

申请日：2019-09-25

Applicant: Arm Limited

Inventor： Fernando Garcia Redondo ,  Shidhartha Das ,  Glen Arnold Rosendale ,  George McNeil Lattimore ,  Mudit Bhargava

IPC: G11C13/00

Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.

公开(公告)号：US10607659B2

公开(公告)日：2020-03-31

申请号：US15960405

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Shidhartha Das ,  George McNeil Lattimore ,  Brian Tracy Cline

IPC: G11C5/06 ,  G11C14/00 ,  G11C8/10 ,  G11C13/00

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

公开(公告)号：US10579126B2

公开(公告)日：2020-03-03

申请号：US15308658

申请日：2015-03-13

Applicant: ARM LIMITED

Inventor： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/324

Abstract: An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.