公开(公告)号：US06801469B2

公开(公告)日：2004-10-05

申请号：US10644107

申请日：2003-08-20

申请人： Timothy B. Cowles

发明人： Timothy B. Cowles

IPC分类号： G11C700

CPC分类号： G11C17/18 ,  G11C17/16 ,  G11C2207/105

摘要： As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

摘要翻译： 作为用于存储器件的反熔丝电路的一部分，本发明的优选示例性实施例提供了用于向该抗熔丝提供电压的反熔丝和接触焊盘之间的直接连接。 接触垫还用作存储器件的至少另一部分的电压源。 在存在于焊盘处的电压会损坏电路或导致电路不正确地读取反熔丝的状态的情况下，耦合到反熔丝的至少一个电路与其暂时隔离。 接触垫在进程内存储器件的探针级期间可用，但一旦器件被封装，则可以防止接触该接触垫。 在生产过程的后端，可以通过第二焊盘访问抗熔丝，其中第二焊盘与抗熔丝进行电连接。

公开(公告)号：US06700416B2

公开(公告)日：2004-03-02

申请号：US10371374

申请日：2003-02-19

申请人： Timothy B. Cowles

发明人： Timothy B. Cowles

IPC分类号： H03K522

CPC分类号： H03K5/08 ,  G01R19/16519 ,  G01R19/16557 ,  G01R19/16595 ,  G01R31/30 ,  G01R31/31721

摘要： An improved input buffer circuit and method configured for voltage detection is provided that can facilitate use of a mid-level voltage for testing purposes. An exemplary input buffer configured for voltage detection comprises a reference generator and a multi-state detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. The multi-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to the two reference voltages, provide output signals to three output terminals representing a high, low and mid-level state of operation. An exemplary input buffer circuit can comprise two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements. In addition, the input buffer can provide for multiple operations from the same die pad without requiring the addition of command pins.

摘要翻译： 提供了一种改进的输入缓冲电路和配置用于电压检测的方法，其可以便于使用中级电压进行测试。 配置用于电压检测的示例性输入缓冲器包括参考发生器和多状态检测器。 参考发生器被配置为产生要作为输入信号提供给多状态检测器的至少两个参考电压。 多状态检测器被适当地配置为接收输入参考信号，并且通过将输入参考信号与两个参考电压进行比较，将输出信号提供给表示高，低和中等级操作状态的三个输出端子。 示例性输入缓冲器电路可以包括以背对背布置配置并共享公共节点的两个差分对晶体管，从而导致较低的电流要求。 此外，输入缓冲器可以提供来自相同管芯焊盘的多个操作，而不需要添加命令引脚。

公开(公告)号：US06665826B2

公开(公告)日：2003-12-16

申请号：US09877897

申请日：2001-06-08

申请人： Timothy B. Cowles

发明人： Timothy B. Cowles

IPC分类号： G11C2900

CPC分类号： G01R31/3016

摘要： An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.

摘要翻译： 集成电路包括连接到第一外部引脚的第一外部引脚和输入缓冲器。 输入缓冲器包括输出端子和第一测试模式输入端子，其适于响应于第一测试模式信号而禁用输出端子。 一种用于测试集成电路的方法，所述集成电路包括第一外部引脚和输入缓冲器，包括在第一指定时间向所述第一外部引脚提供第一外部输入信号，并且在第二指定时间之后禁用所述输入缓冲器 第一个指定的时间。

公开(公告)号：US06657905B1

公开(公告)日：2003-12-02

申请号：US10147037

申请日：2002-05-17

申请人： Jeffrey Koelling ,  Timothy B. Cowles

发明人： Jeffrey Koelling ,  Timothy B. Cowles

IPC分类号： G11C700

CPC分类号： G11C17/18 ,  G11C5/145

摘要： A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.

摘要翻译： 在反熔丝编程期间使用的引导电路具有钳位电路，其被设计成防止编程电压被集成电路中的其他部件不必要地限制。 引导电路连接在外部接口（例如接合焊盘）和内部线路之间，并且当编程电压被直接施加到内部线路（即，不通过外部接口）时被激活。 当被激活时，钳位电路允许向内部线路施加适当且足够高的电压，以正确编程反熔丝，同时还夹紧在外部接口处看到的电压量。

公开(公告)号：US06552596B2

公开(公告)日：2003-04-22

申请号：US09927587

申请日：2001-08-10

申请人： Timothy B. Cowles ,  Victor Wong

发明人： Timothy B. Cowles ,  Victor Wong

IPC分类号： H03K301

CPC分类号： H03K19/0016 ,  H03K19/007

摘要： An input buffer receives an external input signal during an active mode and a low-power mode. The input buffer includes a switching system to switch the input buffer between multiple conductive paths such that current consumed by the input buffer during the low-power mode is substantially less than current consumed by the buffer during the active mode.

摘要翻译： 输入缓冲器在活动模式和低功耗模式期间接收外部输入信号。 输入缓冲器包括切换系统，以在多个导电路径之间切换输入缓冲器，使得在低功率模式期间由输入缓冲器消耗的电流基本上小于在激活模式期间由缓冲器消耗的电流。

公开(公告)号：US06493286B1

公开(公告)日：2002-12-10

申请号：US10126730

申请日：2002-04-19

申请人： Brendan N. Protzman ,  Timothy B. Cowles

发明人： Brendan N. Protzman ,  Timothy B. Cowles

IPC分类号： G11C800

CPC分类号： G11C11/409 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22

摘要： A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of the READ operation. A latch is set during the active command in order to set a node voltage which allows the IO pull-up signal to end upon the firing of the column access signal. The invention allows improvement in tRCD parameter, and allows digit line pairs to separate without unwanted line sharing with the IO lines prior to reading of the first bit of a data burst. The result is a more accurate and error-free read of a first bit of data during a READ sequence.

公开(公告)号：US6128237A

公开(公告)日：2000-10-03

申请号：US455365

申请日：1999-12-06

申请人： Brian Shirley ,  Timothy B. Cowles

发明人： Brian Shirley ,  Timothy B. Cowles

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.

摘要翻译： 一种用于降低由与有源字线相关联的多个读出放大器的同时激活而产生的峰值电流的方法和装置，而不会降低半导体存储器件的操作速度。 存储器阵列包括访问存储器单元的字线和跟踪字线，用于通过在每个读出放大器或读出放大器组的激活之后引入延迟并且在激活下一个读出放大器或组之前，顺序激活连接到数字线的读出放大器 的感测放大器，使得与有源字线相关联的所有数字线的感测放大器的激活总时间被扩展，但不超过激活整个字线所需的时间。

公开(公告)号：US6049502A

公开(公告)日：2000-04-11

申请号：US388086

申请日：1999-08-30

申请人： Timothy B. Cowles ,  Jeffrey P. Wright

发明人： Timothy B. Cowles ,  Jeffrey P. Wright

IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C11/406 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C29/26 ,  G11C7/1015 ,  G11C7/1072 ,  G11C8/12 ,  G11C2029/2602

摘要： In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.

公开(公告)号：US5946265A

公开(公告)日：1999-08-31

申请号：US891557

申请日：1997-07-11

申请人： Timothy B. Cowles

发明人： Timothy B. Cowles

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C16/04

CPC分类号： G11C7/1072 ,  G11C7/1018 ,  G11C7/1024

摘要： An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latch a memory address from external address lines and internally generates additional memory addresses. The integrated circuit memory can output data in a continuous stream while new rows of the memory are accessed. A method and circuit are described for outputting a burst of data stored in a first row of the memory while accessing a second row of the memory.

摘要翻译： 描述了可以在高数据速度下操作的集成电路存储器件。 存储器设备可以在突发存取操作中存储或从存储器检索数据。 突发操作从外部地址线锁存存储器地址，并在内部生成额外的存储器地址。 当访问存储器的新行时，集成电路存储器可以连续流输出数据。 描述了一种方法和电路，用于在访问存储器的第二行时输出存储在存储器的第一行中的数据的突发。

公开(公告)号：US5940315A

公开(公告)日：1999-08-17

申请号：US144457

申请日：1998-09-01

申请人： Timothy B. Cowles

发明人： Timothy B. Cowles

IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C8/00

CPC分类号： G11C5/063

摘要： Disclosed is a method and apparatus for connecting the wordlines of memory arrays to respective row decoders in a manner which reduces the physical space required for implementing a memory device. The wordlines of a first memory array are connected directly to an adjacent row decoder. Metal straps, which connect across every other wordline of the first memory array, are used to connect the row decoder to the wordlines of another memory array not adjacent to the row decoder. By utilizing the same row decoders for multiple arrays via the metal straps, the number of row decoders required for a memory bank can be reduced, thereby reducing the overall physical space necessary for implementation of the memory device. The use of metal for the straps provides minimal effect on the access timing of the wordlines connected to the row decoders via the metal straps, and the strapping of only every other wordline of each array provides sufficient space between the straps to prevent them from shorting together.

摘要翻译： 公开了一种用于以减少实现存储器件所需的物理空间的方式将存储器阵列的字线连接到各行解码器的方法和装置。 第一存储器阵列的字线直接连接到相邻行解码器。 连接在第一存储器阵列的每个其它字线上的金属带用于将行解码器连接到不与行解码器相邻的另一个存储器阵列的字线。 通过使用通过金属带的多个阵列的相同的​​行解码器，可以减少存储体所需的行解码器的数量，从而减少实现存储器件所需的整体物理空间。 使用金属作为带子对通过金属带连接到行解码器的字线的访问时间提供最小的影响，并且每个阵列的每隔一个字线的捆扎提供了带之间的足够空间以防止它们一起短路 。