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    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods
    61.
    发明申请
    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods 审中-公开
    用于制造具有降低的对闩锁敏感性的半导体器件结构和通过该方法形成的半导体器件结构的方法

    公开(公告)号：US20070194403A1

    公开(公告)日：2007-08-23

    申请号：US11360345

    申请日：2006-02-23

    申请人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    发明人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L21/76

    CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

    摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体方法和器件结构。 该方法包括在衬底的半导体材料中形成沟槽，其第一侧壁设置在也在衬底的半导体材料中定义的一对掺杂阱之间。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩蔽沟槽的基底，随后去除暴露在部分屏蔽的基底上的衬底的半导体材料，以限定加深沟槽的变窄的第二侧壁。 加深的沟槽填充有介电材料以限定用于内置于掺杂阱中的器件的沟槽隔离区域。 填充沟槽加深的介质材料增强了闩锁抑制。

    Dual gated finfet gain cell
    62.
    发明申请
    Dual gated finfet gain cell 有权
    双门控finfet增益单元

    公开(公告)号：US20060008927A1

    公开(公告)日：2006-01-12

    申请号：US11221118

    申请日：2005-09-07

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

    IPC分类号： H01L21/00

    CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

    摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

    摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。

    Wrap-around gate field effect transistor
    64.
    发明申请
    Wrap-around gate field effect transistor 有权
    环绕栅场效应晶体管

    公开(公告)号：US20050127466A1

    公开(公告)日：2005-06-16

    申请号：US10732958

    申请日：2003-12-11

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    IPC分类号： H01L21/334 ,  H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/76 ,  H01L29/00

    CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

    摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

    摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

    Horizontal memory gain cells
    65.
    发明申请
    Horizontal memory gain cells 失效
    水平记忆增益细胞

    公开(公告)号：US20050286293A1

    公开(公告)日：2005-12-29

    申请号：US10879815

    申请日：2004-06-29

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

    IPC分类号： G11C11/00 ,  G11C13/02 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/17 ,  H01L27/108 ,  H01L27/10861 ,  H01L27/10873 ,  Y10S977/742

    摘要： A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.

    摘要翻译： 用于存储器电路的增益单元，由多个增益单元形成的存储器电路，以及制造这种增益单元和存储器电路的方法。 存储增益单元包括存储电容器，与存储电容器电耦合以对存储电容器进行充电和放电以定义存储的电荷的写入装置和读取装置。 读取装置包括一个或多个半导体碳纳米管，每个碳纳米管电耦合在源极和漏极之间。 每个半导体碳纳米管的一部分由读取栅极和存储电容器选通，从而调节从源极到漏极流过每个半导体碳纳米管的电流。 电流与存储电容器存储的电荷成比例。 在某些实施例中，存储器增益单元可以包括多个存储电容器。

    Method of forming FinFET gates without long etches
    68.
    发明申请
    Method of forming FinFET gates without long etches 有权
    在没有长时间刻蚀的情况下形成FinFET栅极的方法

    公开(公告)号：US20050202607A1

    公开(公告)日：2005-09-15

    申请号：US10798907

    申请日：2004-03-11

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Hofak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Hofak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831

    摘要： A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that have contributed to the difficulty of forming FinFETs using conventional techniques. In particular, a sacrificial seed layer, from which sidewalls can be accurately grown, is first deposited over a silicon fin. Once the sacrificial seed layer is etched away, the sidewalls can be surrounded by another disposable layer. Etching away the sidewalls will result in cavities being formed that straddle the fin, and gate conductor material can then be deposited within these cavities. Thus, the height and thickness of the resulting FinFET gate can be accurately controlled by avoiding a long direction etch down the entire height of the fin.

    摘要翻译： 用于形成用于FinFET的栅极的方法使用一系列选择性沉积的侧壁与其它牺牲层一起形成可以准确可靠地形成栅极的空腔。 该技术避免了长时间的定向蚀刻步骤，以形成使用常规技术有助于形成FinFET的困难的栅极的临界尺寸。 特别地，首先在硅片上沉积可以精确地生长侧壁的牺牲种子层。 一旦牺牲种子层被蚀刻掉，侧壁可以被另一个一次性层包围。 蚀刻侧壁将导致跨过翅片形成的空腔，然后栅极导体材料可以沉积在这些空腔内。 因此，通过避免沿翅片的整个高度的长方向蚀刻，可以精确地控制所得FinFET栅极的高度和厚度。