公开(公告)号：US06100135A

公开(公告)日：2000-08-08

申请号：US266352

申请日：1999-03-11

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91 ,  H01L28/55 ,  H01L28/92

Abstract: The present invention is a method of manufacturing a high density capacitor for use in semiconductor memories. High etching selectivity between BPSG (borophosphosilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a capacitor with a plurality of horizontal fins. First, a nitride layer is formed on a semiconductor substrate. A first conductive layer is then formed on the nitride layer. A stacked layer consists of BPSG and silicon oxide formed on the first conductive layer. Then a contact hole is formed in the stacked layer, the first conductive layer and the nitride layer. A highly selective etching is then used to etch the BPSG sublayers of the stacked layer. Next, a second polysilicon layer is formed in the contact hole and on the stacked layer, subsequently, a dielectric layer is formed on the second polysilicon layer. Then photolithography and etching processes are used to define the storage node. Next a third conductive layer is deposited over the dielectric layer, the stacked layer, and the first conductive layer, subsequently, performing an anisotropic etching to etch the third conductive layer and the second conductive layer. The stacked layer is removed by BOE solution. A dielectric film is then formed along the surface of the first, second, and third conductive layers. Finally, a fourth conductive layer is formed on the dielectric film. Thus, a crown-fin shaped capacitor with higher capacitance is fabricated.

Abstract translation: 本发明是制造用于半导体存储器的高密度电容器的方法。 使用BPSG（硼磷硅酸玻璃）和CVD氧化物（化学气相沉积氧化物）之间的高蚀刻选择性来制造具有多个水平翅片的电容器。 首先，在半导体衬底上形成氮化物层。 然后在氮化物层上形成第一导电层。 堆叠层由形成在第一导电层上的BPSG和氧化硅组成。 然后在堆叠层，第一导电层和氮化物层中形成接触孔。 然后使用高选择性蚀刻来蚀刻堆叠层的BPSG子层。 接下来，在接触孔和层叠层上形成第二多晶硅层，随后在第二多晶硅层上形成介电层。 然后使用光刻和蚀刻工艺来定义存储节点。 接下来，在电介质层，堆叠层和第一导电层上沉积第三导电层，随后执行各向异性蚀刻以蚀刻第三导电层和第二导电层。 堆叠层由BOE溶液除去。 然后沿着第一，第二和第三导电层的表面形成电介质膜。 最后，在电介质膜上形成第四导电层。 因此，制造具有较高电容的冠状电容器。

公开(公告)号：US6100127A

公开(公告)日：2000-08-08

申请号：US990167

申请日：1997-12-12

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/336

CPC classification number: H01L27/0266 ,  H01L21/823443 ,  H01L27/0288 ,  H01L27/088

Abstract: A MOS transistor with a self-aligned silicide and a lightly doped drain ballast resistor for ESD protection on a semiconductor substrate is formed with the method in the present invention. The ESD protection devices in a ESD protective region are formed at the same time with the forming of the NMOS, PMOS, or both in a functional region. The transistors with a lightly doped drain (LDD) structure and an ultra-shallow junction can be manufactured. The short channel effect and it's accompanying hot carrier effect is eliminated. ESD damage from external connections to the integrated circuits are kept from the densely packed devices. The self-aligned silicide (salicide) technology employed in the present invention for forming low resistance contacts provides high operation speed with low heat generation. Integrated circuits with ESD hardness and high circuit operation speed of the functional devices are provided by the semiconductor manufacturing process employing the method disclosed.

Abstract translation: 通过本发明的方法形成具有自对准硅化物的MOS晶体管和用于半导体衬底上ESD保护的轻掺杂漏极镇流电阻。 ESD保护区域中的ESD保护器件在功能区域中形成NMOS，PMOS或两者的同时形成。 可以制造具有轻掺杂漏极（LDD）结构和超浅结的晶体管。 消除了短通道效应和伴随的热载体效应。 外部连接到集成电路的ESD损坏与密集封装的设备保持一致。 用于形成低电阻触点的本发明中使用的自对准硅化物（自对准硅化物）技术提供了高的运行速度和低的发热。 通过使用所公开的方法的半导体制造工艺提供具有ESD硬度和功能器件的高电路操作速度的集成电路。

公开(公告)号：US6084265A

公开(公告)日：2000-07-04

申请号：US50540

申请日：1998-03-30

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8247 ,  H01L29/76

CPC classification number: H01L27/11521

Abstract: The present invention proposes a novel structure of nonvolatile memories with recessed floating gates. A plurality of field oxides is formed on a semiconductor substrate. Buried bit lines are formed in the semiconductor substrate and beneath the field oxides. Between the field oxides over the buried bit lines, trenched floating gates are formed in the semiconductor substrate. Tunnel dielectrics are formed between the trenched floating gates and the semiconductor substrate. The interpoly dielectric is formed over the field oxides and the trenched floating gates and the control gates are formed on the interpoly dielectric. Because of the large area of the recessed tunnel dielectric and the recessed length of the channel, high-density shallow trench contactless nonvolatile memories can be achieved.

Abstract translation: 本发明提出了具有凹入浮动栅极的非易失性存储器的新颖结构。 在半导体衬底上形成多个场氧化物。 掩埋位线形成在半导体衬底中并在场氧化物之下。 在掩埋位线之间的场氧化物之间，在半导体衬底中形成沟槽的浮动栅极。 在沟槽的浮动栅极和半导体衬底之间形成隧道电介质。 在场氧化物之间形成互聚电介质，并且沟槽浮置栅极和控制栅极形成在多晶硅电介质上。 由于凹槽隧道电介质的面积大，通道凹陷长，所以可实现高密度浅沟槽非接触非易失性存储器。

公开(公告)号：US6074932A

公开(公告)日：2000-06-13

申请号：US14866

申请日：1998-01-28

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: The method for forming a trench isolation includes the steps as follows. At first, a first pad layer is formed over the semiconductor substrate and a stacked layer is formed over the first pad layer. An opening is then defined in the first pad layer and the stacked layer. A portion of the first pad layer is removed to have an undercut region under the stacked layer. A second pad layer is formed on an exposed portion of the semiconductor substrate under the opening and the undercut region. Then a buffer layer within the undercut region and a sidewall structure on the stacked layer are formed. A portion of the second pad layer uncovered by the sidewall structure is removed. A portion of the semiconductor substrate uncovered by the stacked layer and the second pad layer is then removed to form a trench. A first insulator layer is formed over the trench and within the undercut region. Thus a trench structure with a first insulator layer can be formed.

Abstract translation: 形成沟槽隔离的方法包括以下步骤。 首先，在半导体衬底上形成第一衬垫层，并且在第一衬垫层上形成堆叠层。 然后在第一衬垫层和堆叠层中限定开口。 去除第一垫层的一部分以在堆叠层下面具有底切区域。 第二衬垫层形成在半导体衬底的开口部和底切区域的露出部分上。 然后形成底切区域内的缓冲层和堆叠层上的侧壁结构。 去除了被侧壁结构覆盖的第二垫层的一部分。 然后去除未被堆叠层和第二焊盘层覆盖的半导体衬底的一部分以形成沟槽。 第一绝缘体层形成在沟槽之上和底切区域内。 因此，可以形成具有第一绝缘体层的沟槽结构。

公开(公告)号：US6069031A

公开(公告)日：2000-05-30

申请号：US13694

申请日：1998-01-26

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8238 ,  H01L27/02 ,  H01L21/336

CPC classification number: H01L21/82385 ,  H01L21/823814 ,  H01L27/0266

Abstract: The process includes the following steps. At first, an isolation region in the semiconductor substrate is formed to separate the semiconductor substrate into a PMOS region, a NMOS region, and an ESD protective region. Gate structures are then formed on the PMOS region, the NMOS region, and the ESD protective region. A doping process is performed to the NMOS region and the ESD protective region, with first dopants for a lightly doped region in the semiconductor substrate. Another doping process is performed to the PMOS region and the ESD protective region, with second dopants for a PMOS anti-punchthrough region and an ESD double diffused region. Spacer structures are formed around the gate structures. The NMOS region and the ESD protective region are then doped with third dopants, for a n-junction region in the semiconductor substrate uncovered by the gate structures. The PMOS region is doped with fourth dopants for a p-junction region in the semiconductor substrate uncovered by the gate structures. Finally, a thermal process is performed to the semiconductor substrate to activate the first dopants, the second dopants, the third dopants, the fourth dopants.

Abstract translation: 该过程包括以下步骤。 首先，形成半导体衬底中的隔离区以将半导体衬底分离成PMOS区，NMOS区和ESD保护区。 然后在PMOS区域，NMOS区域和ESD保护区域上形成栅极结构。 对NMOS区域和ESD保护区域进行掺杂处理，其中第一掺杂剂用于半导体衬底中的轻掺杂区域。 对PMOS区域和ESD保护区域进行另一种掺杂工艺，其中第二掺杂剂用于PMOS反穿通区域和ESD双重扩散区域。 在栅极结构周围形成间隔结构。 NMOS区域和ESD保护区域然后掺杂有第三掺杂剂，对于未被栅极结构覆盖的半导体衬底中的n结区域。 PMOS区域掺杂有半导体衬底中未被栅极结构覆盖的p结区域的第四掺杂剂。 最后，对半导体衬底进行热处理以激活第一掺杂剂，第二掺杂剂，第三掺杂剂，第四掺杂剂。

公开(公告)号：US6034396A

公开(公告)日：2000-03-07

申请号：US14867

申请日：1998-01-28

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/76 ,  H01L21/265 ,  H01L21/302

CPC classification number: H01L29/66613 ,  H01L21/28525 ,  H01L21/76895 ,  H01L29/66537 ,  H01L29/7834

Abstract: The transistor structure in the present invention has a recessed region on the top surface of the semiconductor substrate. The transistor has a gate insulator within the recessed region and the gate insulator has a gate space within. A gate electrode is formed within and over the gate space. The transistor has a first insulator layer between the gate electrode and the semiconductor substrate. A semiconductor layer is formed over a portion of the semiconductor substrate uncovered by the gate insulator and the gate electrode. The transistor has a junction region with third type dopants. The junction region is located within the semiconductor substrate under a region uncovered by the gate insulator and the gate electrode. An extended junction region with first type dopants is also created. The extended junction region is located within the semiconductor substrate under the gate insulator. The transistor also has an anti-punchthrough region with second type dopants. The anti-punchthrough region is located within the semiconductor substrate under the gate electrode.

Abstract translation: 本发明的晶体管结构在半导体衬底的顶表面上具有凹陷区域。 晶体管在凹陷区域内具有栅极绝缘体，栅极绝缘体内部具有栅极空间。 在栅极空间中形成栅电极。 晶体管在栅电极和半导体衬底之间具有第一绝缘体层。 半导体层的一部分形成在半导体衬底的未被栅极绝缘体和栅电极覆盖的部分上。 晶体管具有与第三类型掺杂剂的结区。 结区域位于半导体衬底的未被栅极绝缘体和栅极电极覆盖的区域之下。 还产生了具有第一类型掺杂剂的延伸结区。 延伸的结区位于栅极绝缘体下面的半导体衬底内。 晶体管还具有带有第二类掺杂剂的抗穿通区域。 抗穿透区域位于栅电极下方的半导体衬底内。

公开(公告)号：US6008087A

公开(公告)日：1999-12-28

申请号：US2607

申请日：1998-01-05

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: The present invention includes forming a pad oxide layer on a substrate. A silicon nitride layer is deposited on the pad oxide. Then, an etching process is used to etch the silicon nitride layer, pad oxide. Subsequently, a silicon oxynitride layer is formed on the substrate. An undoped polysilicon layer is deposited on the silicon nitride layer and silicon oxynitride layer. Subsequently, polysilicon side wall spacers are formed. Then, the silicon nitride layer is removed to expose the pad oxide. Then, a blanket ion implantation is carried out to implant dopant into the side wall spacers, and through the pad oxide or the silicon oxynitride layer into the substrate. An oxide layer is deposited on the polysilicon side wall spacers. Then, a chemical mechanical polishing (CMP) is performed for planarization. A further silicon oxynitride layer is grown at the top of the polysilicon side wall spacers. Next, a doped polysilicon layer is formed on the oxide, polysilicon side wall spacers as word line.

Abstract translation: 本发明包括在衬底上形成衬垫氧化物层。 氮化硅层沉积在衬垫氧化物上。 然后，使用蚀刻工艺来蚀刻氮化硅层，衬垫氧化物。 接着，在基板上形成氧氮化硅层。 在氮化硅层和氮氧化硅层上沉积未掺杂的多晶硅层。 随后，形成多晶硅侧壁间隔物。 然后，去除氮化硅层以暴露衬垫氧化物。 然后，进行覆盖式离子注入以将掺杂剂注入到侧壁间隔物中，并且通过焊盘氧化物或氮氧化硅层进入衬底。 氧化物层沉积在多晶硅侧壁间隔物上。 然后进行化学机械抛光（CMP）进行平面化。 在多晶硅侧壁间隔物的顶部生长另外的氮氧化硅层。 接下来，在氧化物，多晶硅侧壁间隔物上形成掺杂多晶硅层作为字线。

公开(公告)号：US5986305A

公开(公告)日：1999-11-16

申请号：US50669

申请日：1998-03-30

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/66598 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66651 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/66545 ,  Y10S257/90

Abstract: An ultra-short channel device with an inverse-T gate lightly-doped drain (ITLDD) structure is disclosed. The present invention includes a semiconductor substrate, which includes a top surface; a source region formed in the semiconductor substrate; and a drain region formed in the semiconductor substrate spaced from the source region by a channel region. Further, the present invention also includes an inverse-T shaped silicon region formed over the semiconductor substrate, wherein the inverse-T shaped silicon region is approximately disposed within the area of the channel region; and a sidewall insulating region abutting to a sidewall of the inverse-T shaped silicon region. A first conductive region is formed on the top surface of the inverse-T shaped silicon region, and a second conductive region is formed on the top surface of the source region. Also, a third conductive region is formed on the top surface of the drain region.

Abstract translation: 公开了具有逆T栅极轻掺杂漏极（ITLDD）结构的超短沟道器件。 本发明包括半导体衬底，其包括顶表面; 形成在所述半导体衬底中的源区; 以及形成在半导体衬底中的漏极区，其通过沟道区与源极区间隔开。 此外，本发明还包括形成在半导体衬底上的反T形硅区域，其中逆T形硅区域大致设置在沟道区域的区域内; 以及与反T形硅区域的侧壁邻接的侧壁绝缘区域。 第一导电区域形成在逆T形硅区域的顶表面上，并且在源极区域的顶表面上形成第二导电区域。 此外，在漏极区域的顶表面上形成第三导电区域。

公开(公告)号：US5966612A

公开(公告)日：1999-10-12

申请号：US995569

申请日：1997-12-22

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L28/82 ,  H01L28/92 ,  H01L27/10814 ,  H01L27/10852

Abstract: A new structure of a capacitor for a DRAM is disclosed herein. The structure of the capacitor includes a mushroom shape first storage node, a dielectric layer and a second storage node. The mushroom shape first storage node includes a base portion that is formed of polysilicon. A plurality of mushroom neck portions located on the base portion. A plurality of roof portions are connected on the tops of the mushroom neck portions. The dielectric layer is conformally covered the surface of the mushroom shape storage node. The second storage node encloses the surface of the dielectric layer. The formation of the mushroom shape capacitor includes forming a first conductive layer over a wafer. Then, an undoped hemispherical grains silicon (HSG-silicon) is formed on the first conductive layer. The HSG-silicon is separated along the grain boundaries to expose a portion of the first conductive layer. Next, the exposed first conductive layer is etched by using the HSG-silicon layer as a mask. A dielectric layer is then deposited on the exposed surface of the first conductive layers, and the HSG-silicon. A second conductive layer is formed over the dielectric layer.

Abstract translation: 这里公开了用于DRAM的电容器的新结构。 电容器的结构包括蘑菇形状的第一存储节点，介质层和第二存储节点。 蘑菇形状的第一存储节点包括由多晶硅形成的基部。 位于基部上的多个蘑菇颈部。 多个屋顶部分连接在蘑菇颈部的顶部上。 电介质层保形地覆盖蘑菇形状存储节点的表面。 第二存储节点包围介质层的表面。 蘑菇形电容器的形成包括在晶片上形成第一导电层。 然后，在第一导电层上形成未掺杂的半球状晶粒硅（HSG-硅）。 沿着晶界分离HSG-硅以露出第一导电层的一部分。 接下来，通过使用HSG-硅层作为掩模来蚀刻暴露的第一导电层。 然后将介电层沉积在第一导电层和HSG-硅的暴露表面上。 在电介质层上形成第二导电层。

公开(公告)号：US5930622A

公开(公告)日：1999-07-27

申请号：US954412

申请日：1997-10-20

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L28/91 ,  H01L28/92

Abstract: A method for forming a double-crown shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first doped polysilicon layer (118) over a semiconductor substrate (110), wherein at least a portion of the first doped polysilicon layer communicates to the substrate. A silicon oxide layer (119) is formed on the first doped polysiliocn layer, followed by removing a portion of the silicon oxide layer. After forming a first silicon nitride spacer (122) on sidewall of the silicon oxide layer, a portion of the first doped polysihocn layer is etched using the first silicon nitride spacer as a mask, thereby forming a recessed cavity (124) in the first doped polysiliocn layer. The recessed cavity and a space surrounded by the first silicon nitride spacer are refilled with a second silicon nitride layer (126). Next, the second silicon oxide layer is removed using the first silicon nitride spacer and the second silicon nitride layer as a mask, and the first doped polysilicon layer is further removed using the first silicon nitride spacer and the second silicon nitride layer as an etch mask. After forming a second doped polysilicon spacer (128) on sidewalls of the first silicon nitride spacer and the first doped polysilicon layer, the second silicon nitride layer and the first silicon nitride spacer are removed. Finally, a dielectric layer (136) is formed on the first doped polysilicon layer and the second doped polysiliocn spacer, and a conductive layer (138) is then formed on the dielectric layer.

Abstract translation: 公开了一种用于形成动态随机存取存储单元的双冠形电容器的方法。 该方法包括在半导体衬底（110）上形成第一掺杂多晶硅层（118），其中第一掺杂多晶硅层的至少一部分与衬底通信。 在第一掺杂聚硅氧烷层上形成氧化硅层（119），然后除去氧化硅层的一部分。 在氧化硅层的侧壁上形成第一氮化硅间隔物（122）之后，使用第一氮化硅间隔物作为掩模蚀刻第一掺杂多晶硅层的一部分，从而在第一掺杂多晶硅层中形成凹腔（124） 聚硅氧烷层。 凹陷腔和由第一氮化硅间隔物围绕的空间用第二氮化硅层（126）重新填充。 接下来，使用第一氮化硅间隔物和第二氮化硅层作为掩模去除第二氧化硅层，并且使用第一氮化硅间隔物和第二氮化硅层作为蚀刻掩模进一步去除第一掺杂多晶硅层 。 在第一氮化硅间隔物和第一掺杂多晶硅层的侧壁上形成第二掺杂多晶硅间隔物（128）之后，去除第二氮化硅层和第一氮化硅间隔物。 最后，在第一掺杂多晶硅层和第二掺杂聚硅氧烷间隔物上形成电介质层（136），然后在电介质层上形成导电层（138）。