公开(公告)号：US20100125719A1

公开(公告)日：2010-05-20

申请号：US12274560

申请日：2008-11-20

申请人： Mark Joseph Hickey ,  Adam James Muff ,  Matthew Ray Tubbs ,  Charles David Wait

发明人： Mark Joseph Hickey ,  Adam James Muff ,  Matthew Ray Tubbs ,  Charles David Wait

IPC分类号： G06F9/40

CPC分类号： G06F9/30098 ,  G06F9/3016 ,  G06F9/3832

摘要： A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.

摘要翻译： 一种电路布置和方法支持指令目标历史的寄存器地址索引，由此由指令使用的寄存器地址使用先前目标寄存器地址的目标历史表和由目标历史表中的索引值提供的索引进行解码 指示。 指令可以包括标识先前使用的寄存器地址的至少一个索引值。 在执行指令期间，从指令中检索索引，然后使用索引从目标历史表中检索一个寄存器地址。

公开(公告)号：US20090300335A1

公开(公告)日：2009-12-03

申请号：US12132115

申请日：2008-06-03

申请人： Adam James Muff ,  Matthew Ray Tubbs

发明人： Adam James Muff ,  Matthew Ray Tubbs

IPC分类号： G06F9/302 ,  G06F7/58

CPC分类号： G06F9/3851 ,  G06F9/30014 ,  G06F9/30181

摘要： A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG. In many instances, an instruction executed by an execution unit may be able to perform an arithmetic operation using both an operand specified by the instruction and a pseudorandom number generated by the PRNG during the execution of the instruction, so that the generation of the pseudorandom number and the performance of the arithmetic operation occur during a single pass of an execution unit.

摘要翻译： 电路布置和方法将基于硬件的伪随机数生成器（PRNG）耦合到执行单元，使得由PRNG生成的伪随机数可以被选择性地输出到执行单元，以在执行指令期间用作操作数， 执行单元。 PRNG可以耦合到操作数多路复用器的输入，该输入输出到执行单元的操作数输入，使得由提供给执行单元的指令提供的操作数被PRNG生成的伪随机数选择性地重写。 此外，提供给执行单元的指令提供的覆盖操作数可以用作PRNG的种子值。 在许多情况下，执行单元执行的指令可以在执行指令期间使用由指令指定的操作数和由PRNG生成的伪随机数来执行算术运算，从而生成伪随机数 并且算术运算的执行在执行单元的单次通过期间发生。

公开(公告)号：US20090240920A1

公开(公告)日：2009-09-24

申请号：US12050721

申请日：2008-03-18

申请人： Adam James Muff ,  Matthew Ray Tubbs

发明人： Adam James Muff ,  Matthew Ray Tubbs

IPC分类号： G06F9/30

CPC分类号： G06F9/30072 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3885

摘要： An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional write instruction identifies a condition as well as data to be tested against that condition. The data is tested against that condition, and the result of the test is used to selectively enable or disable a write to a target associated with the data dependent conditional write instruction. Then, a write is attempted while the write to the target is enabled or disabled such that the write will update the contents of the target only when the write is selectively enabled as a result of the test. By doing so, dependencies are typically avoided, as is use of an architected condition register that might otherwise introduce branch prediction mispredict penalties, enabling improved performance with z-buffer test and similar types of algorithms.

摘要翻译： 执行单元支持仅当满足特定条件时将数据写入目标的数据相关条件写指令。 在一个实现中，依赖于数据的条件写入指令识别条件以及针对该条件进行测试的数据。 根据该条件测试数据，并且测试结果用于选择性地启用或禁用对与数据相关条件写指令相关联的目标的写入。 然后，当对目标的写入被启用或禁用时，尝试写入，以便只有当作为测试的结果有选择地启用写入时，写入才会更新目标的内容。 通过这样做，通常可以避免依赖关系，因为使用可能会导致分支预测错误处理的架构条件寄存器，可以通过z缓冲区测试和类似类型的算法实现改进的性能。

公开(公告)号：US20120303691A1

公开(公告)日：2012-11-29

申请号：US13556464

申请日：2012-07-24

申请人： Adam James Muff ,  Matthew Ray Tubbs

发明人： Adam James Muff ,  Matthew Ray Tubbs

IPC分类号： G06F7/58

CPC分类号： G06F9/3851 ,  G06F9/30014 ,  G06F9/30181

摘要： A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG.

摘要翻译： 电路布置和方法将基于硬件的伪随机数生成器（PRNG）耦合到执行单元，使得由PRNG生成的伪随机数可以被选择性地输出到执行单元，以在执行指令期间用作操作数， 执行单元。 PRNG可以耦合到操作数多路复用器的输入，该输入输出到执行单元的操作数输入，使得由提供给执行单元的指令提供的操作数被PRNG生成的伪随机数选择性地覆盖。 此外，提供给执行单元的指令提供的覆盖操作数可以用作PRNG的种子值。

公开(公告)号：US20090228690A1

公开(公告)日：2009-09-10

申请号：US12045313

申请日：2008-03-10

申请人： Adam James Muff ,  Matthew Ray Tubbs

发明人： Adam James Muff ,  Matthew Ray Tubbs

IPC分类号： G06F9/38

CPC分类号： G06F9/30014 ,  G06F7/4873 ,  G06F7/535 ,  G06F9/30065 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859 ,  G06F2207/5355 ,  G06F2207/5356

摘要： An “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in addition to disabling the register write enable of these instructions. By doing so, the latency of the algorithm is reduced and the performance is increased without the complexity and potential poor performance of compare and branch instructions that might otherwise be required.

摘要翻译： 迭代细化算法的“提前退出”除了禁用寄存器写入之外，还通过有效禁用更新指令的写依赖性停止之后的读取以及禁止这些指令的寄存器写使能，对于算法的其余部分 启用这些指令。 通过这样做，降低了算法的等待时间，并且性能得到提高，而没有另外需要的比较和分支指令的复杂性和潜在的差的性能。

公开(公告)号：US20090228689A1

公开(公告)日：2009-09-10

申请号：US12045243

申请日：2008-03-10

申请人： Adam James Muff ,  Matthew Ray Tubbs

发明人： Adam James Muff ,  Matthew Ray Tubbs

IPC分类号： G06F9/38

CPC分类号： G06F9/30014 ,  G06F7/4873 ,  G06F7/535 ,  G06F9/30065 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859 ,  G06F2207/5355 ,  G06F2207/5356

摘要： A programmable “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in addition to disabling the register write enable of these instructions. In addition, programmable logic is provided to enable a custom early exit condition to be specified for the iterative refinement algorithm so that the underlying hardware can be configured for optimal execution of particular iterative refinement algorithms. By doing so, the latency of the algorithm is reduced and the performance is increased without the complexity and potential poor performance of compare and branch instructions that might otherwise be required.

摘要翻译： 迭代细化算法的可编程的“提前退出”是通过有效禁用更新指令的写依赖性停止之后的读取，以及禁用这些指令的其余部分的这些指令的寄存器写使能，除了禁止寄存器 写这些指令的使能。 此外，提供可编程逻辑以使得能够为迭代细化算法指定定制的早期退出条件，使得可以配置底层硬件以优化特定迭代细化算法的执行。 通过这样做，降低了算法的等待时间，并且性能得到提高，而没有另外需要的比较和分支指令的复杂性和潜在的差的性能。

公开(公告)号：US20180211638A1

公开(公告)日：2018-07-26

申请号：US15415569

申请日：2017-01-25

申请人： Tolga Ozguner ,  Jeffrey Powers Bradford ,  Miguel Comparan ,  Gene Leung ,  Adam James Muff ,  Ryan Scott Haraden ,  Christopher Jon Johnson

发明人： Tolga Ozguner ,  Jeffrey Powers Bradford ,  Miguel Comparan ,  Gene Leung ,  Adam James Muff ,  Ryan Scott Haraden ,  Christopher Jon Johnson

IPC分类号： G09G5/395 ,  G06T1/60 ,  G06T1/20 ,  G09G5/00 ,  G02B27/01 ,  G03H1/00

CPC分类号： G09G5/395 ,  G02B27/0103 ,  G02B27/017 ,  G02B2027/014 ,  G02B2027/0178 ,  G02B2027/0187 ,  G03H1/0005 ,  G03H2001/0088 ,  G06F1/163 ,  G06F3/011 ,  G06F12/0207 ,  G06F12/0862 ,  G06F12/121 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/455 ,  G06F2212/6026 ,  G06T1/20 ,  G06T1/60 ,  G09G3/003 ,  G09G2360/121 ,  Y02D10/13

摘要： Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.

公开(公告)号：US20150379376A1

公开(公告)日：2015-12-31

申请号：US14318135

申请日：2014-06-27

申请人： Adam James Muff ,  John Allen Tardif ,  Susan Carrie ,  Mark J. Finocchio ,  Kyungsuk David Lee ,  Christopher Douglas Edmonds ,  Randy Crane

发明人： Adam James Muff ,  John Allen Tardif ,  Susan Carrie ,  Mark J. Finocchio ,  Kyungsuk David Lee ,  Christopher Douglas Edmonds ,  Randy Crane

IPC分类号： G06K9/62

CPC分类号： G06K9/6267 ,  G06K9/00973 ,  G06K9/6282

摘要： Embodiments are disclosed that relate to processing image pixels. For example, one disclosed embodiment provides a system for classifying pixels comprising retrieval logic; a pixel storage allocation including a plurality of pixel slots, each pixel slot being associated individually with a pixel, where the retrieval logic is configured to cause the pixels to be allocated into the pixel slots in an input sequence; pipelined processing logic configured to output, for each of the pixels, classification information associated with the pixel; and scheduling logic configured to control dispatches from the pixel slots to the pipelined processing logic, where the scheduling logic and pipelined processing logic are configured to act in concert to generate the classification information for the pixels in an output sequence that differs from and is independent of the input sequence.

摘要翻译： 公开了涉及处理图像像素的实施例。 例如，一个公开的实施例提供了一种用于对包括检索逻辑的像素进行分类的系统; 包括多个像素时隙的像素存储分配，每个像素时隙与像素相关联，其中所述检索逻辑被配置为使所述像素被分配到输入序列中的所述像素时隙中; 流水线处理逻辑被配置为针对每个像素输出与像素相关联的分类信息; 以及调度逻辑，被配置为控制从像素时隙到流水线处理逻辑的调度，其中调度逻辑和流水线处理逻辑被配置为一致地起作用以产生与输出序列不同且独立于的输出序列中的像素的分类信息 输入序列。