公开(公告)号：US06877086B1

公开(公告)日：2005-04-05

申请号：US09705678

申请日：2000-11-02

申请人： Darrell D. Boggs ,  Douglas M. Carmean ,  Per H. Hammarlund ,  Francis X. McKeen ,  David J. Sager ,  Ronak Singhal

发明人： Darrell D. Boggs ,  Douglas M. Carmean ,  Per H. Hammarlund ,  Francis X. McKeen ,  David J. Sager ,  Ronak Singhal

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3861

摘要： Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

摘要翻译： 使用重放队列在处理器中重新安排多个微操作。 处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地安排执行指令并将每个指令分派到执行单元。 检查器耦合到执行单元以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

公开(公告)号：US06633963B1

公开(公告)日：2003-10-14

申请号：US09618489

申请日：2000-07-18

申请人： Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

发明人： Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

IPC分类号： G06F1206

CPC分类号： G06F12/1491 ,  G06F12/1441

摘要： A processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that stores configuration settings. The configuration settings include a plurality of subsystem memory range settings defining memory zones. The access transaction also includes access information. A multi-memory zone access checking circuit, coupled to the configuration storage, checks the access transaction using at least one of the configuration settings and the access information. The multi-memory zone access checking circuit generates an access grant signal if the access transaction is valid.

摘要翻译： 具有正常执行模式和隔离执行模式的处理器生成访问事务。 访问事务使用存储配置设置的配置存储进行配置。 配置设置包括定义存储器区域的多个子系统存储器范围设置。 访问事务还包括访问信息。 耦合到配置存储器的多存储器区域访问检查电路使用配置设置和访问信息中的至少一个来检查访问事务。 如果访问事务有效，则多存储区访问检查电路生成访问许可信号。

公开(公告)号：US5428807A

公开(公告)日：1995-06-27

申请号：US79498

申请日：1993-06-17

申请人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowny

发明人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowny

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3863

摘要： There is provided a mechanism for propagating exception conditions in a computer system when instructions are subject to exception conditions. The apparatus includes a set of data registers for storing data manipulated by the instructions of the computer system, and a set of state registers for storing speculative states of data manipulated by the instructions, there being one state register associated with each data register. Furthermore, the apparatus includes a logic circuit, coupled to the set of state registers, for propagating the states from a source one of the state registers to a destination one of the state registers, if data stored in an associated source one of the data registers are used as a source for an associated destination one of data registers, and if data stored in the source data register were manipulated by a particular instruction subject to an exception condition.

摘要翻译： 当指令受到异常条件的限制时，提供了一种在计算机系统中传播异常情况的机制。 该装置包括一组数据寄存器，用于存储由计算机系统的指令操纵的数据，以及一组状态寄存器，用于存储由指令操纵的数据的推测状态，存在与每个数据寄存器相关联的一个状态寄存器。 此外，该装置包括耦合到一组状态寄存器的逻辑电路，用于将状态从状态寄存器中的一个状态寄存器传播到状态寄存器的目的地寄存器，如果数据存储在相关源中的一个数据寄存器 被用作相关联的目的地数据寄存器的源，并且如果存储在源数据寄存器中的数据被受异常条件的特定指令操纵。

公开(公告)号：US4947358A

公开(公告)日：1990-08-07

申请号：US325928

申请日：1989-03-20

申请人： Virginia C. Lamere ,  Elaine H. Fite ,  Francis X. McKeen

发明人： Virginia C. Lamere ,  Elaine H. Fite ,  Francis X. McKeen

IPC分类号： G06F7/00 ,  G06F7/60 ,  G06F7/74 ,  G06F7/76 ,  G06F9/42

CPC分类号： G06F7/74 ,  G06F7/607

摘要： A normalizer that identifies the bits that are set in input data and generates output signals representing the positions of the set bits in the input data. The normalizer has a device arranged to receive an n-bit signal. Each of the bits of the n-bit signal are either set or clear. The normalizer operates iteratively, and during each iteration: determines an end most set bit; generates a signal representing position information for this end most set bit; and clears the end most set bit that was identified during the immediately previous iteration. The normalizer also includes a novel bit counter that provides a count of the number of bits set in the input data.

公开(公告)号：US4888679A

公开(公告)日：1989-12-19

申请号：US142794

申请日：1988-01-11

申请人： Tryggve Fossum ,  Ricky C. Hetherington ,  David B. Fite, Jr. ,  Dwight P. Manley ,  Francis X. McKeen ,  John E. Murray

发明人： Tryggve Fossum ,  Ricky C. Hetherington ,  David B. Fite, Jr. ,  Dwight P. Manley ,  Francis X. McKeen ,  John E. Murray

IPC分类号： G06F12/06 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8069 ,  G06F12/0207 ,  G06F12/0855 ,  G06F9/3455 ,  G06F9/383

摘要： A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from memory. In response to a prefetch request, the cache is checked for a "miss" and if the cache does not include the required block, a refill request is sent to the main memory. The main memory is configured into a plurality of banks and has a capability of processing multiple references. Therefore the different banks can be referenced simultaneously to prefetch multiple blocks of vector data. Preferably a cache bypass is provided to transmit data directly to the vector processor as the data from the main memory are being stored in the cache. In a preferred embodiment, a vector processor is added to a digital computing system including a scalar processor, a virtual address translation buffer, a main memory and a cache. The scalar processor includes a microcode interpreter which sends a vector load command to the vector processing unit and which also generates vector prefetch requests. The addresses for the data blocks to be prefetched are computed based upon the vector address, the length of the vector and the "stride" or spacing between the addresses of the elements of the vector.

摘要翻译： 适用于标量处理的主存储器和缓存器与矢量处理器结合使用以响应于矢量加载指令的识别发出预取请求。 为包含要从存储器加载的向量的元素的每个块发出相应的预取请求。 响应于预取请求，检查缓存是否存在“未命中”，并且如果高速缓存不包括所需的块，则向主存储器发送补充请求。 主存储器被配置成多个存储体并且具有处理多个引用的能力。 因此，可以同时引用不同的库来预取多个向量数据块。 优选地，提供高速缓存旁路以将数据直接发送到向量处理器，因为来自主存储器的数据正被存储在高速缓存中。 在优选实施例中，将向量处理器添加到包括标量处理器，虚拟地址转换缓冲器，主存储器和高速缓存的数字计算系统。 标量处理器包括微代码解释器，其向向量处理单元发送向量加载命令，并且还生成向量预取请求。 要预取的数据块的地址是基于向量地址，向量的长度和向量元素的地址之间的“stride”或间距来计算的。