公开(公告)号：US20070057288A1

公开(公告)日：2007-03-15

申请号：US11556352

申请日：2006-11-03

申请人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

发明人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

IPC分类号： H01L31/00

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

摘要翻译： 半导体器件包括其中具有凹部的半导体衬底。 栅极绝缘体设置在凹部中的基板上。 该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。 源极/漏极区域设置在邻近凹部的衬底中。 凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。 源极/漏极区域可以包括邻近凹部的较轻掺杂部分。 还讨论了相关制造方法。

公开(公告)号：US07122431B2

公开(公告)日：2006-10-17

申请号：US10754676

申请日：2004-01-09

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Sung-Young Lee ,  Hye-Jin Cho ,  Eun-Jung Yun ,  Shin-Ae Lee ,  Chang-Woo Oh ,  Jeong-Dong Choe

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Sung-Young Lee ,  Hye-Jin Cho ,  Eun-Jung Yun ,  Shin-Ae Lee ,  Chang-Woo Oh ,  Jeong-Dong Choe

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/00 ,  H01L21/20 ,  H01L21/425

CPC分类号： H01L29/66651 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/0653

摘要： Methods of forming a unit cell of a metal oxide semiconductor (MOS) transistor are provided. An integrated circuit substrate is formed. A MOS transistor is formed on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. The first and second spaced apart buffer regions are formed beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.

摘要翻译： 提供了形成金属氧化物半导体（MOS）晶体管的晶胞的方法。 形成集成电路基板。 在集成电路基板上形成MOS晶体管。 MOS晶体管具有源极区，漏极区和栅极。 栅极在源极区域和漏极区域之间。 第一和第二间隔开的缓冲区形成在源极区域和漏极区域之间以及源极区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

公开(公告)号：US20060192255A1

公开(公告)日：2006-08-31

申请号：US11396819

申请日：2006-04-03

申请人： Seong-Ho Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee

发明人： Seong-Ho Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee

IPC分类号： H01L29/76

CPC分类号： H01L21/76831 ,  H01L21/28114 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

摘要： A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

公开(公告)号：US07026688B2

公开(公告)日：2006-04-11

申请号：US11119786

申请日：2005-05-02

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

公开(公告)号：US20050189583A1

公开(公告)日：2005-09-01

申请号：US11119786

申请日：2005-05-02

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

摘要翻译： 集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。 活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。 栅电极围绕通道并延伸穿过至少一个通道。 还提供了一对源极/漏极区域。 通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。 预激活图案包括彼此交替堆叠的一系列通道间层和通道层。 源极/漏极区域在预活化图案的相对端处在衬底上形成。 选择性地去除通道间层以形成隧道。 在隧道中形成栅电极并围绕通道。

公开(公告)号：US20050133881A1

公开(公告)日：2005-06-23

申请号：US11011258

申请日：2004-12-13

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L29/00 ,  H01L29/06

CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/66659

摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

摘要翻译： 半导体器件采用非对称埋层绝缘层及其制造方法。 半导体器件包括下半导体衬底。 上硅图案位于下半导体衬底上。 上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。 栅电极与上硅图案电绝缘，并且在沟道区域上相交。 位线和单元电容器分别电连接到源极区域和漏极区域。 掩埋绝缘层插入在漏区和下半导体衬底之间。 掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

公开(公告)号：US20050098094A1

公开(公告)日：2005-05-12

申请号：US10982554

申请日：2004-11-05

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Mia-Sang Kim ,  Sung-Ming Kim

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Mia-Sang Kim ,  Sung-Ming Kim

IPC分类号： H01L21/336 ,  C30B23/00 ,  H01L21/331 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L29/1079 ,  H01L29/78

摘要： Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer. Then, a transistor may be formed on the semiconductor substrate. The sacrificial layer may be a crystalline semiconductor formed by an epitaxial growth technology.

摘要翻译： 本发明的实施例包括部分绝缘的场效应晶体管及其制造方法。 根据一些实施例，通过顺序堆叠底部半导体层，牺牲层和顶部半导体层来形成半导体衬底。 可以去除牺牲层以在底部半导体层和顶部半导体层之间形成掩埋间隙区域。 然后，可以在半导体衬底上形成晶体管。 牺牲层可以是通过外延生长技术形成的晶体半导体。