公开(公告)号：US08293820B2

公开(公告)日：2012-10-23

申请号：US11875800

申请日：2007-10-19

申请人： Shigeo Nishiguchi ,  Hideki Iijima ,  Naoyuki Yoshikawa ,  Kiyoshi Kato ,  Yukihiro Nemoto ,  Reijirou Nishida

发明人： Shigeo Nishiguchi ,  Hideki Iijima ,  Naoyuki Yoshikawa ,  Kiyoshi Kato ,  Yukihiro Nemoto ,  Reijirou Nishida

IPC分类号： C08L63/02

CPC分类号： C25D13/06 ,  C09D5/4496 ,  C25D13/16

摘要： A cationic electrodeposition coating composition comprising a cationic resin (A) and a blocked polyisocyanate (B) obtained by reaction between a polyisocyanate compound (b1) with two or more isocyanate groups, castor oil (b2) and a blocking agent (b3). The cationic electrodeposition coating composition has excellent throwing power, suitability for electrodeposition onto hot dip galvanized steel sheets, finished appearance and corrosion resistance.

摘要翻译： 一种阳离子电沉积涂料组合物，其包含阳离子树脂（A）和通过多异氰酸酯化合物（b1）与两个或多个异氰酸酯基团反应获得的封端多异氰酸酯（B），蓖麻油（b2）和封闭剂（b3）。 阳离子电沉积涂料组合物具有优异的抛光力，适用于电沉积到热镀锌钢板上，成品外观和耐腐蚀性。

公开(公告)号：US08222676B2

公开(公告)日：2012-07-17

申请号：US11783092

申请日：2007-04-05

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： H01L23/48

CPC分类号： H01L29/4238 ,  H01L27/0207 ,  H01L29/42384 ,  Y10S257/908

摘要： A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.

摘要翻译： 晶体管和半导体集成电路，其布局面积减小。 通过以更高的密度布置接触来实现晶体管的面积减小。 具体地说，在夹杂有一对杂质区域和栅极电极604的晶体管中，杂质区域之一具有各自的接触孔（第一接触孔601和第二接触孔602），另一个杂质区域具有接触孔 （第三接触孔603），并且每个包括用于接触的边缘的接触孔601至603或区域605至607的触点布置成除了栅电极604之外的三角形晶格。

公开(公告)号：US20120161127A1

公开(公告)日：2012-06-28

申请号：US13331645

申请日：2011-12-20

申请人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

发明人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

IPC分类号： H01L29/78

CPC分类号： H01L27/1156 ,  G11C11/404 ,  H01L27/1225

摘要： The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.

摘要翻译： 第一晶体管包括作为源极和漏极的第一和第二电极，以及与第一沟道形成区域重叠的第一栅电极，其间设置有绝缘膜。 第二晶体管包括作为源极和漏极的第三和第四电极以及设置在第二栅电极和第三栅极之间的第二沟道形成区，其中设置在第二沟道形成区和第二栅电极之间的绝缘膜 并且在第二通道形成区域和第三栅电极之间。 第一和第二沟道形成区域包含氧化物半导体，并且第二电极连接到第二栅电极。

公开(公告)号：US08190949B2

公开(公告)日：2012-05-29

申请号：US13113228

申请日：2011-05-23

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： G06F11/00

CPC分类号： G06F11/3447 ,  G06F11/3409 ,  G06F2201/81

摘要： An operations management apparatus which acquires performance information for each of a plurality of performance items from a plurality of controlled units and manages operation of the controlled units includes a correlation model generation unit which derives a correlation function between a first series of performance information that indicates time series variation about a first element and a second series of performance information that indicates time series variation about a second element, generates a correlation model between the first element and the second element based on the correlation function, and obtains the correlation model for each element pair of the performance information, and a correlation change analysis unit which analyzes a change in the correlation model based on the performance information acquired newly which has not been used for generation of the correlation model.

公开(公告)号：US08148215B2

公开(公告)日：2012-04-03

申请号：US12484273

申请日：2009-06-15

申请人： Kiyoshi Kato ,  Yoshiyuki Kurokawa

发明人： Kiyoshi Kato ,  Yoshiyuki Kurokawa

IPC分类号： H01L21/84

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7881

摘要： A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating surface, active layer side ends (110) are tapered. This makes the thickness of a first insulating film (106), which is formed by a thermal oxidization process, at the active layer side ends (110) the same as the thickness of the rest of the first insulating film. Therefore local thinning of the first insulating film does not take place. Moreover, the tapered active layer side ends hardly tolerate electric field concentration at active layer side end corners (111). Accordingly, a leak current from an electric charge accumulating layer (107) to the active layer (105) is reduced to improve the electric charge holding characteristic. As a result, the first insulating film can be further made thin to obtain a high performance non-volatile memory that operates at a low voltage and consumes less power.

摘要翻译： 提供了从电荷累积层到有源层的泄漏电流减小的非易失性存储器以及制造非易失性存储器的方法。 在由形成在具有绝缘表面的基板（101）上的由半导体薄膜制成的非易失性存储器中，有源层侧端（110）是锥形的。 这使得通过热氧化工艺形成的第一绝缘膜（106）在有源层侧端部（110）的厚度与第一绝缘膜的其余部分的厚度相同。 因此，不会发生第一绝缘膜的局部变薄。 此外，锥形有源层侧端部难以容忍有源层侧端角处的电场浓度（111）。 因此，减少了从电荷累积层（107）到有源层（105）的泄漏电流，以改善电荷保持特性。 结果，可以进一步使第一绝缘膜变薄，以获得在低电压下工作并消耗更少功率的高性能非易失性存储器。

公开(公告)号：US20120063207A1

公开(公告)日：2012-03-15

申请号：US13230157

申请日：2011-09-12

申请人： Kiyoshi Kato ,  Toshihiko Saito

发明人： Kiyoshi Kato ,  Toshihiko Saito

IPC分类号： G11C11/24 ,  G11C7/22

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

摘要： An object of one embodiment of the present invention is to miniaturize a semiconductor device. Another object of one embodiment of the present invention is to reduce the area of a driver circuit of a semiconductor device including a memory element. A plurality of cells in which the positions of input terminals and output terminals are fixed is arranged in a first direction, wirings each of which is electrically connected to the input terminal or the output terminal of each cell are stacked over the plurality of cells, and the wirings extend in the same direction as the first direction in which the cells are arranged; thus, a semiconductor device in which a driver circuit is miniaturized is provided.

摘要翻译： 本发明的一个实施例的目的是使半导体器件小型化。 本发明的一个实施例的另一个目的是减小包括存储元件的半导体器件的驱动电路的面积。 其中固定有输入端子和输出端子的位置的多个单元被布置在第一方向上，电连接到每个单元的输入端子或输出端子的布线堆叠在多个单元上，并且 布线沿与布置电池单元的第一方向相同的方向延伸; 因此，提供了其中驱动电路小型化的半导体器件。

公开(公告)号：US20110254538A1

公开(公告)日：2011-10-20

申请号：US13085606

申请日：2011-04-13

申请人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri ,  Kazuma Furutani

发明人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri ,  Kazuma Furutani

IPC分类号： G01R19/00

CPC分类号： G01R31/2601 ,  G01R19/0092

摘要： One object is to provide a method for measuring current by which minute current can be measured. A value of current flowing through an electrical element is not directly measured but is calculated from change in a potential observed in a predetermined period. The method for measuring current includes the steps of: applying a predetermined potential to a first terminal of an electrical element having the first terminal and a second terminal; measuring an amount of change in a potential of a node connected to the second terminal; and calculating, from the amount of change in the potential, a value of current flowing between the first terminal and the second terminal of the electrical element. Thus, the value of minute current can be measured.

摘要翻译： 一个目的是提供一种用于测量可以测量微小电流的电流的方法。 流过电气元件的电流的值不是直接测量的，而是根据在预定周期内观察到的电位的变化计算出的。 用于测量电流的方法包括以下步骤：将预定电位施加到具有第一端子和第二端子的电气元件的第一端子; 测量连接到第二终端的节点的电位变化量; 以及根据所述电位变化量计算在所述电气元件的所述第一端子和所述第二端子之间流动的电流值。 因此，可以测量微小电流的值。

公开(公告)号：US20110246837A1

公开(公告)日：2011-10-06

申请号：US13133718

申请日：2010-10-13

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： G06F11/34

CPC分类号： G06F11/079 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/3452 ,  G06Q10/02

摘要： In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes. The analysis unit 31 performs abnormality detection of the performance information of the system which has been inputted by using the inputted performance information and the correlation model corresponding to the attribute of a period in which the inputted performance information has been acquired.

摘要翻译： 在系统运行管理装置中，降低了在检测未来的故障时提供判定准则时对系统管理员的负担。 系统运行管理装置1包括演奏信息存储单元12，模型生成单元30和分析单元31.演奏信息存储单元12以时间序列存储包括系统中的多种类型的演奏值的演奏信息。 模型生成单元30对于具有多个属性中的一个的多个周期中的每一个，生成包括存储在演奏信息存储单元12中的不同类型的演奏值之间的一个或多个相关性的相关模型。 分析单元31通过使用输入的演奏信息和与已经获取了输入的演奏信息的时段的属性相对应的相关模型来执行已经输入的系统的演奏信息的异常检测。

公开(公告)号：US07975186B2

公开(公告)日：2011-07-05

申请号：US12391435

申请日：2009-02-24

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： G06F11/00

CPC分类号： G06F11/3447 ,  G06F11/3409 ,  G06F2201/81

摘要： An operations management apparatus which acquires performance information for each of a plurality of performance items from a plurality of controlled units and manages operation of the controlled units includes a correlation model generation unit which derives a correlation function between a first series of performance information that indicates time series variation about a first element and a second series of performance information that indicates time series variation about a second element, generates a correlation model between the first element and the second element based on the correlation function, and obtains the correlation model for each element pair of the performance information, and a correlation change analysis unit which analyzes a change in the correlation model based on the performance information acquired newly which has not been used for generation of the correlation model.

摘要翻译： 一种操作管理装置，其从多个受控单位取得多个演奏项目的演奏信息，并管理被控制的单位的动作，包括：相关模型生成部，其将表示时刻的第一系列演奏信息， 关于第一元素的系列变化和指示关于第二元素的时间序列变化的第二系列性能信息，基于相关函数在第一元素和第二元素之间生成相关模型，并获得每个元素对的相关模型 以及相关变化分析单元，其基于未被用于生成相关模型的新获得的性能信息来分析相关模型的变化。

公开(公告)号：US20110148463A1

公开(公告)日：2011-06-23

申请号：US12966513

申请日：2010-12-13

申请人： Kiyoshi Kato ,  Jun Koyama

发明人： Kiyoshi Kato ,  Jun Koyama

IPC分类号： H03K19/173

CPC分类号： H03K19/1733 ,  G11C14/0063 ,  G11C16/02 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/7869 ,  H03K3/356008 ,  H03K3/35606

摘要： A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.

摘要翻译： 提供了一种新颖的非易失性锁存电路和使用非易失性锁存电路的半导体器件。 锁存电路具有环形结构，其中第一元件的输出电连接到第二元件的输入，并且第二元件的输出通过第二晶体管电连接到第一元件的输入端。 使用使用氧化物半导体作为沟道形成区域的半导体材料的晶体管作为开关元件，并且提供电容器以电连接到晶体管的源电极或漏电极，由此锁存电路的数据可以 并且可以形成非易失性锁存电路。