公开(公告)号：US20090279367A1

公开(公告)日：2009-11-12

申请号：US12502932

申请日：2009-07-14

申请人： Chulmin Jung ,  Kang Yong Kim

发明人： Chulmin Jung ,  Kang Yong Kim

IPC分类号： G11C7/10 ,  G11C7/02

CPC分类号： G11C8/12 ,  G11C7/103 ,  G11C8/18

摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

摘要翻译： 公开了诸如涉及固态存储器件的方法和装置。 一种这样的方法包括选择存储器阵列中的多个存储器单元。 确定存储在所选择的多个存储单元中的多个数据位的状态。 在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。 顺序提供多个数据位作为输出。 在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。

公开(公告)号：US07596039B2

公开(公告)日：2009-09-29

申请号：US11706937

申请日：2007-02-14

申请人： Kang Yong Kim ,  Chulmin Jung

发明人： Kang Yong Kim ,  Chulmin Jung

IPC分类号： G11C7/00 ,  G11C7/02

CPC分类号： G11C7/1096 ,  G11C7/00 ,  G11C7/02 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4097 ,  G11C13/004 ,  H03F3/16

摘要： An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

摘要翻译： 输入 - 输出线路读出放大器被配置为通过输入 - 输出信号线将输入数据信号驱动到输出驱动器电路，输入 - 输出线路读出放大器具有输出驱动级，其具有多个不同的可编程输出驱动能力，以定制 读出放大器的输出驱动。

公开(公告)号：US20090059707A1

公开(公告)日：2009-03-05

申请号：US11847559

申请日：2007-08-30

申请人： Chulmin Jung ,  Kang Yong Kim

发明人： Chulmin Jung ,  Kang Yong Kim

IPC分类号： G11C8/12

CPC分类号： G11C8/12 ,  G11C7/103 ,  G11C8/18

摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

公开(公告)号：US07433249B2

公开(公告)日：2008-10-07

申请号：US11347961

申请日：2006-02-06

申请人： Chulmin Jung

发明人： Chulmin Jung

IPC分类号： G11C5/14

CPC分类号： G11C11/4094

摘要： A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced by a feedback and control loop of the equalization voltage generator. The feedback and control loop includes a reference generator circuit to produce a stable, internal reference signal that is clamped at a maximum reference voltage. A comparator of the feedback and control loop compares the internal reference signal with a second voltage, which is proportional to the first voltage. The comparator causes the oscillator to turn on when the second voltage is lower than the reference voltage, and causes the oscillator to turn off when the second voltage is higher than the reference voltage.

摘要翻译： 存储器件包括均衡电压发生器。 均衡电压发生器包括振荡器和电荷泵以产生第一电压，其可以用作互补数字线对的均衡电压。 振荡器由均衡电压发生器的反馈和控制回路产生的振荡器控制信号控制。 反馈和控制回路包括参考发生器电路，以产生稳定的内部参考信号，其被钳位在最大参考电压。 反馈和控制环路的比较器将内部参考信号与第一电压成比例的第二电压进行比较。 当第二电压低于参考电压时，比较器使振荡器导通，并且当第二电压高于参考电压时使振荡器关断。

公开(公告)号：US08638597B2

公开(公告)日：2014-01-28

申请号：US13476368

申请日：2012-05-21

申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

公开(公告)号：US20120230094A1

公开(公告)日：2012-09-13

申请号：US13476368

申请日：2012-05-21

申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

IPC分类号： G11C11/16

CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

公开(公告)号：US20120039111A1

公开(公告)日：2012-02-16

申请号：US13278334

申请日：2011-10-21

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78 ,  H01L45/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US20110299323A1

公开(公告)日：2011-12-08

申请号：US13206550

申请日：2011-08-10

申请人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

发明人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.

摘要翻译： 一种用于将数据写入诸如RRAM存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。 多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。 源极线连接到开关器件，并将一系列存储器单元连接在一起。 此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并通过至少一部分 剩余的RSE连接到所选择的源线。

公开(公告)号：US08072014B2

公开(公告)日：2011-12-06

申请号：US12903301

申请日：2010-10-13

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US07935619B2

公开(公告)日：2011-05-03

申请号：US12774018

申请日：2010-05-05

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.

摘要翻译： 描述了形成电阻式读出存储器的极性依赖开关的方法。 用于形成存储器单元的方法包括在源极接触中比半导体晶体管的位接触更多地注入掺杂剂材料，并且将电阻性感测存储器单元电连接到位触点。 电阻读出存储单元被配置为在电流通过电阻读出存储单元时在高电阻状态和低电阻状态之间切换。