公开(公告)号：US09203420B2

公开(公告)日：2015-12-01

申请号：US14173595

申请日：2014-02-05

Applicant: Innophase, Inc.

Inventor： Xuejun Zhang ,  Yang Xu

IPC: H03M3/00 ,  H03M1/00 ,  H03F3/04 ,  H03M1/08 ,  G05F1/625

CPC classification number: H03M3/50 ,  G05F1/625 ,  G05F3/262 ,  H03F3/04 ,  H03M1/00 ,  H03M1/002 ,  H03M1/0854 ,  H03M1/742 ,  H03M1/747

Abstract: A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.

Abstract translation: 使用适合用于调制器的电流镜的DAC。 实施例包括提供信息信号的电流产生电路; 偏置电流源; 电流镜，其具有连接到电流产生电路和偏置电流源的反射镜输入晶体管，并由偏置电流和变化的电流信号驱动，并且在控制端处具有相应的变化电压信号; 插入在所述反射镜输入晶体管和被配置为限制所述变化的电压信号的带宽的输出镜像晶体管之间的信号整形滤波器; 所述输出镜晶体管被配置为产生带限变化电流信号和镜像偏置电流; 以及连接到输出镜晶体管的镜像偏置电流降低电路，被配置为减少镜像偏置电流。

公开(公告)号：US20150326230A1

公开(公告)日：2015-11-12

申请号：US14275477

申请日：2014-05-12

Applicant: Innophase Inc.

Inventor： Yang Xu ,  Sara Munoz Hermoso

IPC: H03L7/099 ,  H03L7/085

CPC classification number: H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B2200/0074 ,  H03D5/00 ,  H03L7/085 ,  H04L27/227 ,  H04L27/2272

Abstract: A receiver includes a harmonic injection-locked oscillator, which receives an RF modulated signal and provides an output to two parallel signal paths. A fundamental injection-locked oscillator is provided on one of the signal paths. A phase discriminator detects a phase difference between signals that have passed through the first and second signal paths. At least one of the signal paths includes an amplitude limiting circuit. One or more of the signal paths may include an adjustable delay circuit.

Abstract translation: 接收机包括谐波注入锁定振荡器，其接收RF调制信号并向两个并行信号路径提供输出。 在其中一个信号路径上提供基本的注入锁定振荡器。 相位鉴别器检测已经通过第一和第二信号路径的信号之间的相位差。 至少一个信号路径包括限幅电路。 一个或多个信号路径可以包括可调延迟电路。

公开(公告)号：US09083588B1

公开(公告)日：2015-07-14

申请号：US14260021

申请日：2014-04-23

Applicant: Innophase Inc.

Inventor： Yang Xu ,  Sara Munoz Hermoso

IPC: H04L25/00 ,  H04L27/227

CPC classification number: H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B2200/0074 ,  H03D5/00 ,  H03L7/085 ,  H04L27/227 ,  H04L27/2272

Abstract: Adjusting a relative phase within a polar receiver to reduce a DC error, the polar receiver having (i) a harmonic ILO having an RF modulated signal input and a phase-compressed divided-frequency output, (ii) a fundamental ILO connected to the phase-compressed divided-frequency output and having a phase-locking output, (iii) a delay element, and (iv) a phase discriminator connected to the delay element output and to the phase-locking output, and having a phase-detection output representative of a phase difference between signals on the delay output and the phase-locking output.

Abstract translation: 调整极坐标接收机内的相对相位以减少DC误差，极地接收机具有（i）具有RF调制信号输入和相位压缩分频输出的谐波ILO，（ii）连接到相位的基本国际劳工组织 压缩分频输出并具有锁相输出，（iii）延迟元件，以及（iv）连接到延迟元件输出和锁相输出的鉴相器，并具有相位检测输出代表 延迟输出信号与锁相输出之间的相位差。

公开(公告)号：US08941441B2

公开(公告)日：2015-01-27

申请号：US13839462

申请日：2013-03-15

Applicant: Innophase, Inc.

Inventor： Nicolo Testi ,  Xi Li ,  Xuejun Zhang ,  Yang Xu

IPC: H03F3/45

CPC classification number: H03G3/008 ,  H03G1/0029 ,  H03G1/0088 ,  H03G5/14 ,  H03G5/24

Abstract: A low noise amplifier including a variable gain amplifier stage configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to the variable gain amplifier stage, wherein the bandpass filter includes a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component when the load driving signal is of a magnitude large enough to decreases a transconductance of the cross-coupled transistor pair; and, a controller circuit configured to tune the bandpass filter. The filter can be tuned in respect to the frequency and the quality factor Q.

Abstract translation: 一种低噪声放大器，包括可变增益放大器级，其被配置为接受输入信号并提供负载驱动信号; 作为负载连接到可变增益放大器级的可调谐带通滤波器，其中所述带通滤波器包括交叉耦合晶体管对，以及偏置在亚阈值区域中的至少一个交叉耦合补偿晶体管对，其配置成当所述跨导分量 负载驱动信号的幅度足够大以减小交叉耦合晶体管对的跨导; 以及配置为调谐带通滤波器的控制器电路。 滤波器可以根据频率和质量因子Q进行调整。

公开(公告)号：US08917759B2

公开(公告)日：2014-12-23

申请号：US13754853

申请日：2013-01-30

Applicant: Innophase Inc.

Inventor： Yang Xu

IPC: H04B1/38 ,  H04L5/16 ,  H04L27/20 ,  H04L27/227 ,  H04L27/22

CPC classification number: H04L27/2272 ,  H04L27/2071 ,  H04L27/22

Abstract: A transceiver is described. The transceiver includes a first injection-locked oscillator and a second injection-locked oscillator. The transceiver also includes a first phase-locked loop coupled with the first injection-locked oscillator. The first phase-locked loop is configured to generate a first frequency reference. Further, the transceiver includes a second phase-locked loop coupled the second injection-locked oscillator. The second phase-locked loop is configured to generate a second frequency reference. The transceiver includes a mixer configured to receive the first phase-locked loop output and configured to receive said second injection-locked oscillator output. The mixer is also configured to generate a carrier frequency signal based on the first injection-locked oscillator output and the second injection-locked oscillator output. And, the transceiver includes a modulator configured to receive said carrier frequency signal.

Abstract translation: 描述收发器。 收发器包括第一注入锁定振荡器和第二注入锁定振荡器。 收发器还包括与第一注入锁定振荡器耦合的第一锁相环。 第一锁相环被配置为产生第一频率参考。 此外，收发器包括耦合第二注入锁定振荡器的第二锁相环。 第二锁相环被配置为产生第二频率参考。 收发器包括配置成接收第一锁相环输出并被配置为接收所述第二注入锁定振荡器输出的混频器。 混频器还被配置为基于第一注入锁定振荡器输出和第二注入锁定振荡器输出产生载波频率信号。 并且，收发器包括被配置为接收所述载波频率信号的调制器。

公开(公告)号：US08803627B1

公开(公告)日：2014-08-12

申请号：US14095968

申请日：2013-12-03

Applicant: Innophase Inc.

Inventor： Yang Xu ,  Sara Munoz Hermoso ,  Xi Li

IPC: H03C3/00

CPC classification number: H03C5/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958

Abstract: A Direct VCO (DCO) modulation apparatus and method that provides a wideband modulated signal output. The wideband response is obtained via signal processing to counteract a high-pass frequency characteristic as seen from the VCO modulation input. That is, low frequency components of data signals are compensated before being applied to a VCO input. The high-pass characteristic in combination with the compensated signal provides a relatively flat, wideband frequency response of the DCO modulator.

Abstract translation: 一种提供宽带调制信号输出的直接VCO（DCO）调制装置和方法。 通过信号处理获得宽带响应，以抵消来自VCO调制输入的高通频率特性。 也就是说，数据信号的低频分量在施加到VCO输入之前被补偿。 与补偿信号相结合的高通特性提供了DCO调制器的相对平坦的宽带频率响应。

公开(公告)号：US12212387B2

公开(公告)日：2025-01-28

申请号：US18346191

申请日：2023-06-30

Applicant: Innophase, Inc.

Inventor： Yang Xu ,  Nicolo Testi ,  Jongheon Kim

IPC: H04B7/0426 ,  H04L27/26

Abstract: Transceiver integrated circuit suitable for distributed placement across an active antenna unit. ICs with two serial data ports configured to transmit and receive aggregated signal-port IQ data packets with adjacent ICs within a subarray of ICs, or to a beamformer processor. A packet header inspection circuit may identify aggregated signal-port IQ data packets for local processing, and identify received aggregated signal-port IQ data packets for processing by another device.

公开(公告)号：US11532897B2

公开(公告)日：2022-12-20

申请号：US17290681

申请日：2019-11-01

Applicant: Innophase, Inc.

Inventor： Yang Xu ,  Jeffrey Shamblin

IPC: H01Q21/22 ,  H04B1/401 ,  H04B1/44 ,  H04B7/06

Abstract: A configurable array having a plurality of antenna elements arranged in at least four adjacent groups of array elements on a panel array, the first group of elements having an inter-element spacing based on a transmit signal wavelength, a second group of elements having an inter-element spacing based on a receive signal wavelength, and a third and fourth group of elements having an inter-element spacing based on a wavelength between the transmit signal wavelength and the receive signal wavelength.

公开(公告)号：US11528068B2

公开(公告)日：2022-12-13

申请号：US17264776

申请日：2019-07-30

Applicant: Innophase, Inc. ,  Parallel Wireless, Inc.

Inventor： Yang Xu ,  Steven Paul Papa

IPC: H04B7/06 ,  H04B7/0417 ,  H04B7/08

Abstract: Methods disclosed herein may include configuring a plurality of transceiver modules in an antenna array with assigned receive signal weighting factors, the transceiver modules interconnected with high-speed data communication buses, and each transceiver module positioned adjacent to a respective antenna element in the antenna array; configuring the plurality of transceiver modules into inter-communicating module groups by enabling the associated high-speed data communication buses; receiving a plurality of wireless data signals with the plurality of transceiver modules and responsively generating a corresponding plurality of receive baseband data signals; generating a plurality of received beamformed signals by combining subsets of the receive baseband signals within each module group using the assigned receive signal weighting factors by transmitting the receive baseband signals between the transceiver modules within the module group; and demodulating the received beamformed signals.

公开(公告)号：US20220384964A1

公开(公告)日：2022-12-01

申请号：US17772861

申请日：2020-10-28

Applicant: Innophase, Inc.

Inventor： Jeffrey Shamblin ,  Yang Xu ,  Claudio Anzil

IPC: H01Q21/06 ,  H01Q5/307

Abstract: A dual-band, tri-band, or higher-order multi-band array of antenna elements, with each element, or subsets of elements, connected to multiple radios at each antenna port. In one embodiment, an array comprises a 128 element Massive MIMO array having 64 horizontally-polarized (H-pol) and 64 vertically-polarized (V-pol) elements configured to provide dual polarization capability over multiple bands to accommodate highly-configurable simultaneous 4G and 5G operation.