公开(公告)号：US11652059B2

公开(公告)日：2023-05-16

申请号：US17536804

申请日：2021-11-29

Applicant: INTEL CORPORATION

Inventor： Adel Elsherbini ,  Shawna Lift ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/3043 ,  H01L21/4846 ,  H01L24/20

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US20230097714A1

公开(公告)日：2023-03-30

申请号：US17485208

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Beomseok Choi ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

公开(公告)号：US20230095608A1

公开(公告)日：2023-03-30

申请号：US17485250

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Feras Eid ,  Henning Braunisch ,  Thomas L. Sounart ,  Johanna Swan ,  Beomseok Choi ,  Krishna Bharath ,  William J. Lambert ,  Kaladhar Radhakrishnan

IPC: H05K3/14 ,  H05K3/10 ,  H05K3/30 ,  H01L21/768 ,  H01L21/82

Abstract: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.

公开(公告)号：US20220415743A1

公开(公告)日：2022-12-29

申请号：US17358361

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Aleksandar Aleksov ,  Julien Sebot

IPC: H01L23/36 ,  H01L25/065 ,  H01L21/50 ,  H01L27/06 ,  H01L23/00

Abstract: Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

公开(公告)号：US11476554B2

公开(公告)日：2022-10-18

申请号：US16613386

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Sasha Oster ,  Telesphor Kamgaing ,  Erich Ewy ,  Adel Elsherbini ,  Johanna Swan

IPC: H01P3/16 ,  H01P5/02 ,  B60R16/023 ,  H01L23/66 ,  H01L25/18 ,  H01R13/622 ,  H01R13/631 ,  H01R13/646 ,  H05K1/18 ,  H05K5/00 ,  H05K5/02 ,  H05K7/20

Abstract: Embodiments of the invention include dielectric waveguides and connectors for dielectric waveguides. In an embodiment a dielectric waveguide connector may include an outer ring and one or more posts extending from the outer ring towards the center of the outer ring. In some embodiments, a first dielectric waveguide secured within the dielectric ring by the one or more posts. In another embodiment, an enclosure surrounding electronic components may include an enclosure wall having an interior surface and an exterior surface and a dielectric waveguide embedded within the enclosure wall. In an embodiment, a first end of the dielectric waveguide is substantially coplanar with the interior surface of the enclosure wall and a second end of the dielectric waveguide is substantially coplanar with the exterior surface of the enclosure wall.

公开(公告)号：US11282812B2

公开(公告)日：2022-03-22

申请号：US16014319

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Johanna Swan

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/498 ,  H01L23/10 ,  H01L23/367 ,  H01L23/427

Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.

公开(公告)号：US11270947B2

公开(公告)日：2022-03-08

申请号：US16698557

申请日：2019-11-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US20220020716A1

公开(公告)日：2022-01-20

申请号：US17488174

申请日：2021-09-28

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

公开(公告)号：US20210410331A1

公开(公告)日：2021-12-30

申请号：US16911817

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Georgios Dogiamis

IPC: H05K7/20 ,  H05K3/34

Abstract: System-level thermal solutions for integrated circuit (IC) die packages including a heat pipe contiguously integrated with base plate material at the hot interface or with heat sink material at the cold interface. Base plate material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of the heat pipe to form a base plate suitable for interfacing with an IC die package. The contiguous base plate material may offer low thermal resistance in the absence of any intervening joining material (e.g., solder or brazing filler). Solder or brazing filler may also be eliminated from between a heat sink and a heat pipe by depositing wick material directly upon the heat sink with an HTAM technique. The wick material may be then enclosed by attaching a preformed half-open tube.

公开(公告)号：US20210159163A1

公开(公告)日：2021-05-27

申请号：US16696808

申请日：2019-11-26

Applicant: INTEL CORPORATION

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: An integrated circuit (IC) device structure, comprising a host chip having a device layer and one or more first metallization levels over adjacent first and second regions of the device layer. The first metallization levels are interconnected to the device layer. An interconnect chiplet is over the first metallization levels within the first region. The interconnect chiplet comprises a plurality of second metallization levels, and a plurality of third metallization levels over the first metallization levels within the second region and adjacent to the interconnect chiplet. At least one of an interconnect feature dimension or composition differs between one of the second metallization levels and an adjacent one of the third metallization levels.